A new CMOS DC voltage doubler with nonoverlapping switching control is proposed, in order to eliminate the dynamic current loss during switching as well as the threshold voltage drop of the serial switches. The simulated results at 1.5 V show that the maximum power efficiency is improved with about 30%, whereas the efficiency in the low output current region is larger than 5 times compared to the conventional voltage doublers. This proposed CMOS DC voltage doubler can be used as a VPP generator of low voltage DRAM's.

Future high density magnetic recording requires a nanometer spaced head-slider interface, high track seeking velocity and high spindle speed. Such a combination greatly increases the likelihood of slider-disk and slider-particle-disk impact. Furthermore, the impact can generate high flash temperature and leads to data reliability problems, such as partial or full data erasure. This work report a method to conduct controlled experimental investigations into the possibility of such a data erasure even when the temperature is far below the Curie temperature. Results indicate that the high density magnetic transitions are of high likelihood of being affected by the flash temperature. Investigations also extended to micromagnetic modeling of the flash temperature effect. Results suggest that thermally induced local stress can play important roll in the data erasure process. Modeling results also exhibit that smaller grain size and higher recording density are also of higher likelihood of getting the transitions being affected by the flash temperature.

In order to serve traffic hot spots, the hierarchical cellular systems or the hybrid TDMA/CDMA have been proposed, recently. In order to depress the multi-user interference and increase capacity, the forward link power control strategy is adopted in the macrocell/microcell hierarchical cellular system using code division multiple access (CDMA). Its effects are estimated in this paper. Especially, the impact of -th distance power control laws on the forward link outage probability and capacity plane for the hierarchical cellular system are investigated. The coverage area user capacity of the overlaid macrocell/microcell cellular system is obtained. The numerical results and discussions with previous published results are presented in detail.

In this paper, using a standard propagation model, the performance evaluation of a code-division-multiple-access (CDMA) cellular system with high data rate services for the reverse and forward links is investigated. In the approach, we propose "Equivalent Load" to estimate two cases of the system termed as the static analysis and the dynamic analysis. Performance measures of the static analysis obtained include the system capacity plane, outage probability and throughput. Performance measures of the dynamic analysis obtained include the allowed maximum data rate and the constraint set between the load situation and the data rate. We also estimate the effects of the power control on the system.

This paper discusses and clarifies effectiveness of data-driven implementation of protocol handling system to access TINA (Telecommunications Information Networking Architecture) network and internet. TINA is a networking architecture that achieves networking services and management ubiquitously for users and networks. Many TINA related ACTS (Advanced Communication Technologies and Services) projects have been organized in Europe. In Japan, The TINA Trial (TTT) to achieve ATM network management and services based on TINA architectures was done by NTT and several manufactures from April 1997 to April 1999. In these studies and trials, much effort is devoted to development of software based on service architecture and network architecture being standardized in TINA-C (TINA Consortium). In order to achieve TINA environment universally in customers and network sides, we have to consider how to deploy TINA environment onto user side and how to use access transmission capacity as efficiently as possible. Recent technology can easily achieve application and environment downloading from the network side to user side by use of e. g. , JAVA. In accessing the network, there are several possible bottlenecks in information exchange in customer side such as PC processing capability, access protocol handling capability, intra-house wiring bandwidth. Authors, in parallel with TINA software architecture study, have been studying versatile requirements for hardware platform of TINA network. In those studies, we have clarified that the stream-oriented data-driven processor authors have been studying and developing have high reliability, high multiprocessing and multimedia information processing capability. Based on these studies, this paper first shows Von Neumann-based protocol handler is ineffective in case of multiprocessing through mathematical and emulation studies. Then, we show our data-driven protocol handling can effectively realize access protocol handling by emulation study. Then, we describe a result of first step of implementation of data-driven TCP/IP protocol handling. This result proves our TCP/IP hub based on data-driven processor is applicable not only for TINA/CORBA network but normal internet access. Finally, we show a possible customer premises network configuration which resolves bottleneck to access TINA network through ATM access.

A new output driver design called modified asymmetrical slew rate (MASR) output driver was proposed to reduce the simultaneous switching noise without sacrificing switching speed, for high speed and heavy loading applications. The driving capability of the output driver was designed to sink/source 64 mA current @ VOL/VOH = 0.4 V/4.6 V, with 66 pF and 50 Ω loading. When four drivers switch simultaneously, the ground bounce was design to be less than 0.8 V. The performances of the conventional, controlled slew rate (CSR), and MASR output drivers were analyzed by computer simulation. These three types of drivers were implemented with a 0.8 µm CMOS process. The measured ground bounce of the conventional driver is 1.22 V, while the ground bounce of the MASR driver is reduced to 0.72 V. The propagation delays of the conventional and MASR drivers are the same. The performance of the MASR driver is better than that of the CSR driver in all aspects.

The layer3 switch enables us to fast transmit IP datagrams using the cut-through technique. The current layer3 router would become bottleneck in terms of delay performance as the amount of traffic injected into high speed networks gets relatively large. Thus, the layer3 switch should be an important element constructing the next generation Internet backbone. In this paper, we analyze the cut-through rate, the datagram waiting time and the mis-ordered rate of a layer3 switch in case of flow-driven connection setup. In the analysis, by using 3-state Markov modulated Bernoulli process (MMBP), we model the arrival process of IP flow and IP datagram from each source. Furthermore, we investigate impacts of the arrival rate and the average datagram length on the performance.

Low voltage (LV) analog circuit design techniques are addressed in this tutorial. In particular, (i) technology considerations; (ii) transistor model capable to provide performance and power tradeoffs; (iii) low voltage implementation techniques capable to reduce the power supply requirements, such as bulk-driven, floating-gate, and self-cascode MOSFETs; (iv) basic LV building blocks; (v) multi-stage frequency compensation topologies; and (vi) fully-differential and fully-balanced systems.

Accurate current analysis is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, and so on. A charge-based current model for CMOS gates is presented in this paper. The current waveform of a CMOS gate during a transition consists of three components: one occurs when the input changes and the others exist only when the output changes. These three components are characterized by triangular pulses with four parameters which can be easily obtained after timing simulation. This model has been embedded into our switch-level timing simulator to generate the current waveform. The simulated current waveform helps solve the VLSI reliability problems due to electromigration and excess voltage drops in the power buses. When comparing the results obtained by using SPICE with those by our model, we find agreement, especially on the time points at which current pulses occur.

In this paper, the Linear Exponential Quadratic Gaussian with Loop Transfer Recovery (LEQG/LTR) methodology is employed for the design of high performance induction motor servo systems. In addition, we design a speed sensorless induction motor vector controlled driver with both the extended Kalman filter and the LEQG/LTR algorithm. The experimental realization of an induction servo system is given. Compared with the traditional PI and LQG/LTR methods, it can be seen that the system output sensitivity for parameter variations and the rising time for larger command input of the proposed method can be significantly reduced.

A fully on-chip current controlled open-drain output driver using a bandgap reference current generator was designed for high bandwidth DRAMs. It reduces the overhead of receiving a digital code from an external source for the compensation of the temperature and supply voltage variations. The correct value of the current control register is updated at the end of every auto refresh cycle. The operation at the data rate up to 0.8 Gb/s was verified by SPICE simulation using a 0.22 µm triple-well CMOS technology.

A half-swing clocking scheme with a complementary gate and source drive is proposed for a CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of a flip-flop using this scheme is less than half of that using the previous half-swing clocking scheme.

A 32-bit motor-drive-specific microcontroller chip was newly designed, implemented using a 0.8 µm double-metal CMOS process, and its feasibility was successfully tested by applying the fabricated microcontroller chip to a real AC induction motor drive system. The microcontroller chip includes a single-precision floating-point unit, peripheral devices for motor drive, and a memory controller as well as the SPARC V7 CPU. The pipeline scheme and the two-step multiplication method were used in the multiplier of floating-point unit for the best area and speed trade-off, using the standard cell library available for the design. The chip size is 12.7 12.8 mm2, the number of transistors is around 562,000, and the power consumption is 1.69 W at the supply voltage of 5 V and the clock frequency of 30 MHz. Both a standard cell library and a full-custom layout were used in the implementation.

The current Internet does not offer any quality of service guarantees or support to Internet multimedia applications such as Internet telephony and video-conferencing, due to the best-effort nature of the Internet. Their performance may be adversely affected by network congestion. Also, since these applications commonly employ the UDP transport protocol, which lacks congestion control mechanisms, they may severely overload the network and starve other applications. We present an overview of recent research efforts in developing adaptive delivery models for Internet multimedia applications, which dynamically adjust the transmission rate according to network conditions. We classify the approaches used to develop adaptive delivery models with brief descriptions of representative research work. We then evaluate the approaches based on important design issues and performance criteria, such as the scalability of the control mechanism, responsiveness in detecting and reacting to congestion, and ability to accommodate receiver heterogeniety. Some conclusions are developed regarding the suitability of particular design choices under various conditions.

Enhancement of resonance is shown by coupling and summing in sinusoidally driven chaotic neural networks. This resonance phenomenon has a peak at a drive frequency similar to noise-induced stochastic resonance (SR), however, the mechanism is different from noise-induced SR. We numerically study the properties of resonance in chaotic neural networks in the turbulent phase with summing and homogeneous coupling, with particular consideration of enhancement of the signal-to-noise ratio (SNR) by coupling and summing. Summing networks can enhance the SNR of a mean field based on the law of large numbers. Global coupling can enhance the SNR of a mean field and a neuron in the network. However, enhancement is not guaranteed and depends on the parameters. A combination of coupling and summing enhances the SNR, but summing to provide a mean field is more effective than coupling on a neuron level to promote the SNR. The global coupling network has a negative correlation between the SNR of the mean field and the Kolmogorov-Sinai (KS) entropy, and between the SNR of a neuron in the network and the KS entropy. This negative correlation is similar to the results of the driven single neuron model. The SNR is saturated as an increase in the drive amplitude, and further increases change the state into a nonchaotic one. The SNR is enhanced around a few frequencies and the dependence on frequency is clearer and smoother than the results of the driven single neuron model. Such dependence on the drive amplitude and frequency exhibits similarities to the results of the driven single neuron model. The nearest neighbor coupling network with a periodic or free boundary can also enhance the SNR of a neuron depending on the parameters. The network also has a negative correlation between the SNR of a neuron and the KS entropy whenever the boundary is periodic or free. The network with a free boundary does not have a significant effect on the SNR from both edges of the free boundaries.

We show by numerical calculations that a chaotic neuron model driven by a weak sinusoid has resonance. This resonance phenomenon has a peak at a drive frequency similar to that of noise-induced stochastic resonance (SR). This neuron model was proposed from biological studies and shows a chaotic response when a parameter is varied. SR is a noise induced effect in driven nonlinear dynamical systems. The basic SR mechanism can be understood through synchronization and resonance in a bistable system driven by a subthreshold sinusoid plus noise. Therefore, background noise can boost a weak signal using SR. This effect is found in biological sensory neurons and obviously has some useful sensory function. The signal-to-noise ratio (SNR) of the driven chaotic neuron model is improved depending on the drive frequency; especially at low frequencies, the SNR is remarkably promoted. The resonance mechanism in the model is different from the noise-induced SR mechanism. This paper considers the mechanism and proposes possible explanations. Also, the meaning of chaos in biological systems based on the resonance phenomenon is considered.

This report describes AlGaAs/GaAs HBT ICs for 20-Gb/s optical transmission, the preamplifier and optical modulator driver circuits, and those ICs for 10-Gb/s clock extraction circuits, the rectifier and phase shifter circuits. These ICs were fabricated using our developed hetero guard-ring fully self-aligned HBT (HG-FST) fabrication process. The Pt-Ti-Pt-Au multimetal system was also used as a base ohmic metal to reduce base contact resistance, and a high fmax of 105 GHz was obtained. Good results in the HBT IC microwave performances were achieved from the on-wafer measurements. The preamplifiers exhibited the broad bandwidth of 20. 9 GHz. The optical modulator driver performed a sufficiently large output-voltage swing of 4-VP-P at a 20-Gb/s data rate. The rectifier and the phase shifter circuits achieved good operations at 10-Gb/s. These results suggest that these HBT ICs can be applied to 20-Gb/s optical transmission and 10-Gb/s clock extraction systems.

In this paper we propose a comprehensive approach to physical design based on the constraint paradigm. Bounds on the most critical circuit parasitics are automatically generated to help designers and/or physical design tools meet a set of high-level specifications. The constraint generation engine is based on constrained optimization, where various parasitic effects on interconnect and devices are accounted for and dealt with in different manners according to their statistical behavior and their effect on performance.

Small-scale video on demand system will be necessary in the future. Cluster drives, which use optical disk drives, are a good buffer memory for this purpose because the cost per megabyte is low. An ordinary optical cluster drive has many SCSI buses and up to seven optical drives are connected to each SCSI bus. One drive from each bus is assembled to make a group of a cluster drive. The difference betweeen SCSI bus data transfer rate and sustained disk transfer rate enables the cluster drive to be simplified. Several drives on an SCSI bus make a sub-group. The video data is striped onto those sub-groups. When the total data transfer rate from disks within a sub-group exceeds the bus transfer rate, some drives can not acquire the bus. When drives connected to one SCSI bus are not identical, the block size of the data to be recorded on each drive has to be adjusted so that the maximum effective data transfer rate can be obtained. When the cycle times of a slow and fast drive are set identical, the effective data transfer rate is maximum, where one cycle consists of command time, minimum bus free time, disk read time, and bus transfer time.

In this paper,a protocol-based modeling and simulation method of performance evaluation for heavy traffic and transient LAN is proposed. In the method a node on a LAN is modeled as a set of detailed communication protocol models. By parallel and event driven processing of the models, high accuracy and high time-resolution of evaluation of LAN behaviors can be obtained at multi-layer protocols. The LANs at computer education sites have highly loaded peaks, and it is very hard to design large scale educational LANs. Proposed method can be used to evaluate such cases of heavy traffic and transient LAN.