WASMII is a virtual hardware system that executes dataflow algorithms using a dynamically reconfigurable multi-context device with a data driven control mechanism. Although the effectiveness of the system has been evaluated through simulations and using an emulator, implementation of WASMII was infeasible due to the unavailability of such a device. However, the first prototype of a practical dynamically reconfigurable multi-context device called DRL has been developed by NEC, and we developed a reconfigurable test bed using four sample DRL chips. On this board, we have implemented and executed some simple applications of WASMII mechanism. Evaluation results show that the performance of the parallel implementation of WASMII is almost twice as that of a PC with a CPU based on the corresponding technology.

This paper describes special-purpose hardware for large-scale logic simulation, called SP2, which executes an event driven algorithm and can simulate up to sixteen million gates. SP2 was developed, in 1992, for system verification of large-scale computer designs as a successor to SP1, which was developed in 1987. SP2 provides enhanced performance, throughput, and delay accuracy over SP1. Since 1992, SP2 has been widely used for system-level simulation of mainframes, super computers, UNIX servers and microprocessors. It is used as a powerful simulator, in all stages of design verification, or in early stages, before regression testing, by using emulators.

In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.

This paper presents a novel system-level design methodology, called quality-driven design, by which application-specific optimization can be achieved; furthermore the entire functionality can be shared to maximize design reuse. As a case of study, this paper focuses on quality-driven design for video applications and introduces an output quality adaptive approach based on variable bitwidth optimization to explore a new design space. MPEG2 video is used as the driver application to illustrate the potential of the presented methodology. Experimental results show the effectiveness of the methodology.

We developed the new electron gun, which can emit about twice electron in comparison with the conventional gun and could achieve the screen brightness of over 300 cd/m2 even if the ordinal driving circuit is applied. We tried two methods to improve the drive characteristics, and we chose to lower the cathode cut-off voltage. To maintain the resolution, we optimized the triode. And we used the tungsten-coated oxide cathode to guarantee the long life.

This paper presents efficient file management of a hard disk drive embedded digital satellite receiver. The digital broadcasting technology enables multimedia access via broadcasting systems. The amount of digital data to be processed is increased remarkably as compared to the previous analog broadcasting environments. The efficient digital data storage and management technology are discussed in this paper to cope with these changes. The DSR uses a new file system that is designed by considering disk cluster sizes and limited memories in the system, which is more appropriate than that of general Personal Computers. The proposed system enables us to watch broadcasting and to manage multimedia data efficiently.

In this paper a new MOS charge pump architecture is presented, where a clock generator is used in each pump stage of the charge pump circuit to elevate voltage exponentially with stages. This charge pump with a clock level shifter is designed to run at an optimized operation frequency, which can make an excellent compromise between the rise time and the dynamic power dissipation. With less stages than the linear-cascade circuit, the power dissipation and the area of the novel charge pump circuit are markedly decreased. The simulating comparison results based on 1.2 µm CMOS, p-substrate double-poly double-metal process parameters show that the nonlinear charge pump with a high pumping efficiency can supply a steady 1 mA, 16 v output for portable LCDs.

In this letter, we propose new driving methods for designing a driver independent of the current property of Organic Light Emitting Diodes (OLED) displays. The proposed methods are the Look-Up Table (LUT) and the Pulse Width Modulation (PWM). The LUT is used to handle the amount of the current for driving the OLED display panel and the PWM is applied to represent the gray scale on the OLED display panel. In particular, the proposed methods are used for the manufacturing of 1.8" 128 128 dot passive matrix OLED display panel. The designed circuit was fabricated using 0.6 µm, 2-poly, 3-metal CMOS process and applied to the Personal Communication System (PCS) phone successfully.

As technology moves to 600-1000 Gb/sq-in areal densities and deep sub-10 nm head-disk spacing, it is of crucial importance to prevent both the conventionally defined thermal decay and the tribologically induced decay of recorded magnetic signal. This paper reports a novel method for recording and visualizing the signature of the potential tribological decay. The details of the methodology, its working principles, and typical results obtained are presented in this work. The method is based on the introduction of a type of visualizing disks which use a layer of magneto-optical material with low Curie temperature to replace the magnetic layer used in the conventional magnetic media. The method and corresponding setup were used successfully in the visualization of potential decay caused by slider-particle-disk contact, slider-disk contact during track seeking operations, and slider-disk impact during loading and unloading operations.

The interaction between slider, lubricant and disk surface is becoming the most crucial robustness concern of advanced data storage systems. This paper reports comparative studies among various techniques for the measurement of head-disk spacing. It is noticed that the triple harmonic method gives a reading much closer to the reading of the head-disk spacing obtained optically at on-track center case, comparing with the PW50 method. Specially prepared disks with different carbon overcoat thickness (6.5 nm, 11 nm, 16 nm and 22 nm) were also used to study the reliability and repeatability of the triple harmonic method.

This paper proposes a compact, low-power, and rail-to-rail class-B output buffer for driving the large column line capacitance of LCDs. The comparator used as a nonlinear element in feedback path is modified from the current-mirror amplifier, which has area and power advantages. The output buffer was realized in a 0.35 m CMOS process. The active area of the buffer is 8673.5 m2. With a 3.3 V supply, the measured quiescent current is 7.4 A. The settling time for 0.05-3.25 V swing to within 0.2% is 8 s.

In CDMA systems, power control strategy is the most important issue since the capacity of the system is only interference-limited. For a better understanding of the effects of Forward Link Power Control Strategy (FLPCS) on the outage probability in fading environments, this paper has presented a theoretical analysis of forward link in a CDMA cellular system by introducing the τ-th power of distance driven control strategy. Based on the power control, the capacity and outage probability of the system are estimated and discussed. In particular, we consider the impact of fading environments and investigate the "hole" phenomenon. Based on our numerical results, the "hole" points are at the upper bounds of where it is possible to ensure minimization of the maximum value of total Interference-to-Signal Ratio (ISR). At those upper bound points, at least, the power control strategy leads to approximately threefold the capacity compared to the case without power control strategy. It can be concluded that the forward link without power control strategy is a very heavy restriction for the capacity of the CDMA system, especially in environments of significant fading.

An LCD Driver IC includes more than 300 buffer amplifiers on a single chip. The phase compensation capacitors (on-chip Miller capacitors) for the amplifiers are more than 1000 pF and occupy a large chip area. This paper describes a two-gain-stage amplifier in which an on-chip Miller capacitor is not used for phase compensation in an LCD Driver IC. In the proposed amplifier, phase compensation is achieved only by a newly introduced zero, which is formed by the load capacitance and a phase compensation resistor connected between the output of the amplifier and the capacitive load. Designs of the phase compensation resistor and the amplifier before compensation are discussed, considering a typical load capacitance range. The test chip was fabricated. The newly introduced zero successfully stabilized the amplifier. The chip area for the amplifier was reduced by 30-40%, compared with our previously reported one. The current consumption of the amplifier was only 5 µA. The experimental results of the fabricated test chip support that the proposed amplifier is suitable to an LCD driver IC with a smaller chip area.

To understand the characteristics of a multimedia service, such as the large volume of data transfer and real-time constraints, it is necessary to have a performance evaluation tool for an HDD. Our HDD simulator is running on a PC operated on FreeBSD UNIX OS. We first investigate the seek time and the sustained rate of HDDs and then evaluate the performance of an HDD for an experimental VOD system. Applying the experimental results, we find the bottleneck of an HDD, and then suggest what HDDs are to be selected for a VOD system.

This paper describes two kinds of on-chip matched low-noise/driver MMIC amplifiers (LN/D-As) suitable for 2.4-GHz and 5.2-GHz short-range wireless applications. The ICs are fabricated in a 0.18 µm bulk CMOS which has no extra processing steps for enhancing the RF performance. The successful use of the current-reuse topology and interdigitated capacitors (IDCs) enables sufficiently low-noise and high output power operations with low current dissipation despite the chip fabrication in the bulk CMOS leading to large RF substrate and conductor losses. The main measurement results of the two LN/D-As are as follows: a 3.8-dB noise figure (NF) and a 10.1-dB gain under the conditions of 1.8 V and 6 mA, a 3.4-dBm 1-dB gain compressed output power (P1dB) for a 2.4-V voltage supply and a 13-mA operating current for the 2.4-GHz LN/D-A, and a 4.9-dB NF and an 11.1-dB gain with a 1.8 V and 10 mA supply condition, a 2.3-dBm P1dB at 2.4 V and 16 mA for the 5.2-GHz LN/D-A. Both MMICs are suited for low-noise amplifiers and driver amplifiers in 2.4-GHz and 5.2-GHz low-cost, low-power wireless systems such as Bluetooth and hiperLAN.

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage (VOL) to be equal to the reference voltage (VOL.ref) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1 Gb/s. The worst-case variations of VOL.ref and VOL of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of 20 to 90 and a supply voltage range of 2.25 V to 2.75 V, while the worst-case variation of VOL of the conventional output driver was measured to be 24% within the same ranges of temperature and supply voltage.

In program slicing, widget-based event-driven programs are different from conventional programs because of their particular features of object construction infrastructure and event-driven mechanism and asynchronous access of global variables. Therefore conventional slicing techniques cannot be applied to widget-based event-driven programs. To solve this problem, this paper first introduces a set of representing schemes including an object construction tree, an object dependence table, a global variable dependence table and an event-driven program dependence graph, then defines a WbEd slicing criterion through combining three kinds of slicing criteria: instruction criterion, event-loop criterion and obj-attr criterion. And a slicing method is developed based on these slicing criteria. Eventually a widget-based event-driven program slicer wbedSlicer is illustrated to verify the efficiency and correctness of the slicing approach.

We derive an efficient and simple analytical expression for estimating maximum simultaneous switching noise (SSN) on ground distribution networks in CMOS systems. In order to estimate maximum SSN voltages, we use α-power law MOS model and Taylor's series approximation. The accuracy of the proposed expression is verified by comparing the results with those of previous researches and HSPICE simulations under the contemporary process parameters and environmental conditions. The proposed method predicts the maximum SSN values more accurately when compared to existing approaches even in most practical cases such that there exist some output drivers not in transition.

In Master-driven TDD based Bluetooth, active Slaves should always listen in the Master-Slave slots because a Slave can transmit packets only after the master polls the Slave. This paper proposes an efficient power management policy to minimize the receiving power which is unnecessarily wasted in Bluetooth. The proposed policy is not controlled by LM (Link manager) protocol, does not need the information about Master-Slave buffers, and guarantees that Slave is in a receive state at Master's polling time. Therefore, there is no degradation of throughput by the proposed policy. The mathematical analysis is carried out in order to investigate our proposed policy. The numerical results show that the proposed policy significantly reduces power consumption over the nave Bluetooth specification.

EL (Electroluminescent) displays have been applied to automobiles, as their images are very clear and bright. High voltage, high integration and low power dissipation ICs are needed to drive these devices. To meet this, high voltage CMOS ICs using SOI (Silicon On Insulator) substrates are chosen as the driving devices. In this paper, an isolation structure between the output CMOS devices, of high density and high voltage is proposed. Conventional trench dielectric isolation shows degradation of a break down voltage with short distance from trench to source. In this work, the authors make clear the electric field distribution near the isolation, and offer a novel structure of "Field-plate Trench Isolation," which enables to relax the electric field on the silicon surface by shifting a part of electric field into surface oxide. Finally, operation of high voltage and high density, a 200-volt and 32-channel, EL display driver for automotive display panel is confirmed.