The scaled down feature size and the increased frequency of today's deep sub-micron region call for fundamental changes in driver-load models. To be more specific, new driver-load models need to take into consideration the nonlinear behavior of the drivers, the inductance effects of the loads, and the slew rates of the output waveforms. Current driver-load models use the conventional single Ceff (one-ramp) approach and treat the interconnect load as lumped RC networks. Neither the nonlinear property nor the inductance effects were considered. The accuracy of these existing models is therefore questionable. This paper introduces a new multi-ramp driver model that represents the interconnect load as a distributed RLC network. The employed two effective capacitance values capture the nonlinear behavior of the driver. The lossy transmission line approach accounts for the impact of inductance when modeling the driving point interconnect load. The new model shows improvements of 9% in the average delay error and 2.2% in the slew rate error compared to SPICE.

A timing-driven placement algorithm based on path topology analysis is presented. The optimization for path delay is transformed into cell location optimization. The algorithm pays much attention on path topologies and applies an effective force directed method to find cell target locations. Total wire length optimization is combined with the timing-driven placement algorithm. MCNC (Microelectronics Centre of North-Carolina) standard cell benchmarks are experimented and results show that our timing-driven placement algorithm can make the longest path delay improve up to 13% compared with wirelength driven placement.

This article describes a large bandwidth and low distortion line driver in a 0.35-µm CMOS process. The line driver drives a 75 Ω resistive load. Its power consumption is 140 mW from a 3.3 V supply. It has a relatively high -3 dB bandwidth (260 MHz) with good phase margin of about 70 degrees. It shows very low THD (-74.5 dB) when drives the load with a 3.3 V peak to peak sine wave at 10 MHz. This architecture reduces the distortion by locating the input differential pair inside the feedback loop and eliminating the distortion of the feedback transistors, which is dominant source of distortion at high frequencies. Thus, it improves the linearity of the output voltage in comparison with previous designs.

The relation between resonant frequency of micromirror with vertical combdrives and applied voltage between the upper and lower comb teeth was analyzed. Resonant frequency of the micromirror was controlled by stiffness of the torsion hinge. Resonant frequency of the mirror was proportional to the applied voltage between the upper and lower comb teeth at the same tilt angle.

A large-swing, high-driving, low-power, class-AB buffer amplifier, which consists of a high-gain input stage and a unity-gain class-AB output stage, with low variation of quiescent current is proposed. The low power consumption and low variation of the quiescent output current are achieved by using a weak-driving and a strong-driving pseudo-source followers. The high-driving capability is mainly provided by the strong-driving pseudo-source follower whose output transistors are turned off in the vicinity of the stable state to reduce the power consumption and the variation of output current, while the quiescent state is maintained by the weak-driving pseudo-source follower. The error amplifiers with source-coupled pairs of the same type transistors are merged into a single error amplifier to reduce the area of the buffer and the current consumption. An experimental prototype buffer amplifier implemented in a 0.35-µm CMOS technology demonstrates that the circuit dissipates an average static power consumption of only 388.7 µW with the standard deviation of only 3.4 µW, which is only 0.874% at a power supply of 3.3 V, and exhibits the slew rates of 2.18 V/µs and 2.50 V/µs for the rising and falling edges, respectively, under a 300 Ω /150 pF load. Both of the second and third harmonic distortions (HD2 and HD3) are -69 dB at 20 kHz under the same load.

This paper presents a new approach based on current mode circuits for fast and accurate optical level monitoring with wide dynamic range of a gigabit burst-mode laser driver chip. Our proposed solution overcomes the drawbacks that voltage mode implementations show at higher bit rates or in other technologies. The main speed-limiting factor of the level monitoring circuitry is the parasitic capacitance of the back facet monitor photodiode. We propose the use of an active-input current mirror to reduce the impact of this parasitic capacitance. The mirror produces two copies of the photo current, one to be used for the "0" level measurement and another for the "1" level measurement. The mirrored currents are compared to two reference currents by two current comparators. Every reference current needs only one calibration at room temperature. A pattern detection block scans the incoming data for patterns of sufficiently long consecutive 0's or 1's. At the end of such a pattern a valid measurement is present at the output of one of the current comparators. Based on these measurements the digital Automatic Power Control (APC) will adjust the bias (IBIAS) and modulation current (IMOD) setting of the laser driver. Tests show that the chip can stabilize and track the launched optical power with a tolerance of less than 1 dB. In these tests the pattern detection was programmed to sample the current comparators after 5 bytes (32 ns at 1.25 Gbps) of consecutive 1's and 0's. Automatic power control on such short strings of data has not been demonstrated before. Although this laser transmitter was developed for FSAN GPON applications at a speed of 1.25 Gbps upstream, the design concept is generic and can be applied for developing a wide range of burst mode laser transmitters. This chip was developed in a 0.35 µm SiGe BiCMOS process.

The lithography process on the deep trench pattern above the large cavity is proposed to fabricate the MEMS structure. Generally, bubbles generated on the trench patterns when it was baked after coating resist. The probability of the generation of bubbles was reduced by decreasing the backing rate. The fast scanning micromirror with 50.8 kHz resonant frequency was fabricated by controlling the backing rate.

This letter proposes an output driver which reduces simultaneous switching noise without degradation of rise/fall time. At the start of transition period, the driver optimally uses both VDD and VSS current by switching of on-chip bypass capacitors. The proposed driver achieves 27-percent reduction in peak current with faster transition time.

A K-band monolithic driver amplifier with equalizer circuits has been developed. It is necessary for the equalizer circuit to be low losses in the high-frequency range and for its S21 values to increase as the operation frequency increases. In order to realize these features, it is desirable for the equalizer to have element location considering high-frequency current flows. In this paper, we present a novel low-loss, high-pass equalizer circuit layout that has superior characteristics in the high-frequency range. We used a high-pass filter as the equalizer circuit and performed a detailed evaluation of the high-frequency characteristics of the filter circuit test element groups (TEGs) for three layout types. It was found that the best filter circuit layout for the three types consisted of two capacitors and one resistor, placed with parallel connections. The resistor is located at the center and the capacitors are located at both sides of the resistor. This filter is called the CRC-type in this paper. An MMIC test sample, a K-band monolithic amplifier with CRC-type filter circuits, was fabricated. The amplifier had a gain of 21.6 dB, a Rollett stability factor K of 28.9, an input VSWR of 1.63, an output VSWR of 1.92, and a 1 dB compressed output power of 22.6 dBm at 26 GHz.

This paper describes low voltage write driver with pulse adding circuit. The presented write driver is constructed from the main switch circuit with impedance matching and pulse adding circuits and a timing generator. The main switch circuit is voltage type driver with matching resisters for flexible lines between a write driver and a write head. For 1.2 Gbps operation, the flexible lines have to be treated as transmission lines. Furthermore, to achieve steep rise/fall edge, the pulse adding circuits to generate double of supply voltage, +3.3/-3 V, at rise/fall edge have been developed. The write driver was implemented using 0.35 µm BiCMOS process. The die size is 1.2 mm0.6 mm and the measured results achieved tr/tf of less than 0.25 ns, tp of 0.5 ns and Ip of 73 mA.

We developed a compact, 16-channel integrated optical subscriber module for one-fiber bi-directional optical access systems. They can support more subscribers in a limited mounting space. For ultimate compactness, we created 8-channel integrated super-compact optical modules, 4-channel integrated limiting amplifiers, and 4-channel integrated LD drivers for Fast Ethernet. We introduce a new simulation method to analyze the electrical crosstalk that degrades sensitivity of the optical module. A new IC architecture is applied to reduce electrical crosstalk. We manufactured the optical subscriber module with these optical modules and ICs. Experiments confirm that the module offers a sensitivity of -27.3 dBm under 16-channel 125 Mbit/s simultaneous operation.

We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6 V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias (FBB) control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15 µm CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0 V.

A novel multi-phase charge-sharing technique is proposed for the dot-inversion method to reduce AC power consumption of the TFT-LCD column driver without requiring any external capacitor for charge conservation. Simple and easy-to-control circuitry is applied in the proposed method, and the power saving efficiency depends on number of charge phases. Increasing the number of charge phases, the saving power efficiency is also raised. Excluding power dissipation of switches, the power saving efficiency is up to 75% theoretically with infinite phases. For previous work, the maximum power saving efficient is 50% without external capacitor. The HSPICE simulation results including power dissipation of all switches show that the proposed method with seven charge phases (eight-column lines as one group) decreases the power consumption of 23-68% and 10-18%, respectively, compared with original circuit (without any low-power scheme) and previous low-power charge-recycling works.

This paper describes a 51.2 GOPS video recognition processor that provides a cost effective device solution for vision-based intelligent cruise control (ICC) applications. By integrating 128 4-way VLIW (Very Low Instruction Word) processing elements and operating at 100 MHz, the processor achieves to provide a computation power enough for a weather robust lane mark and vehicle detection function written in a high level programming language, to run in video rate, while at the same time it satisfies power efficiency requirements of an in-vehicle LSI. Basing on four basic parallel methods and a software environment including an optimizing compiler of an extended C language and video-based GUI tools, efficient development of real-time video recognition applications that effectively utilize the 128 processing elements are facilitated. Benchmark results show that, this processor can provide a four times better performance compared with a 2.4 GHz general purpose micro-processor.

This paper proposes a retargetable framework for rapid evaluation of processor architecture, which represents abstraction levels of architecture in a hierarchical manner. The basis for such framework is a hierarchical architecture description language, called XR2, which describes architecture at three abstraction levels: instruction set architecture, pipeline architecture and micro-architecture. In addition, a token-level computational model for fast pipeline simulation is proposed, which considers the minimal information required for the given performance measurement of the pipeline. Experimental result shows that token-level simulation is faster than the traditional cycle-accurate one by 50% to 80% in pipeline architecture evaluation.

As the CMOS technology enters the very deep submicron era, inter-wire coupling capacitance becomes the dominant part of load capacitance. The coupling effects have brought new challenges to routing algorithms on both delay estimation and optimization. In this paper, we propose a timing-driven global routing algorithm with consideration of coupling effects. Our two-phase algorithm based on timing-relax method includes a heuristic Steiner tree algorithm to guarantee the timing performance of the initial solution and an optimization algorithm based on coupling-effect-transference. Experimental results are given to demonstrate the efficiency and accuracy of the algorithm.

We've been developing new electron guns for a high brightness CRT. The electron guns were modified to increase the emission current without the increase of the driving voltage. We achieved the high brightness CRT with "low cut-off electron gun" and the gun was successfully introduced into our multimedia CRT. Now we are developing next generation gun or "double drive electron gun" for larger screen CRT. The gun can emit about double current in comparison with the "low cut-off electron gun."

As head-disk spacing is reduced, the effects caused by inter-molecular level interactions between head-slider and disk media are becoming a severe stability concern of head-slider's positioning in both flying height and track following directions. Therefore, there is a need to explore simple but effective methods for characterizing two dimensional (2D) stability. Ideally methods should be easy to implement in both the laboratory and in the quality control of disk drive and component manufacturing. A reading process based in-situ method is explored in this work. The method is simple and can effectively reveal the 2D stability of the head-slider in both laboratory and manufacturing environments. The results obtained also suggest that the observable sway mode vibration of the suspension can be excited earlier than the air-bearing vibration mode, when the flying height is reduced.

We report in this paper, the performance of AlGaN/GaN HFETs in the context of high power, low noise and high temperature operations, along with a comparison of their characteristics with other conventional technologies. Finally, a single stage modulator driver for long haul optical communications is presented as an example of application of the GaN-based devices high power handling capabilities.

It is very difficult to simultaneously achieve power and cost reductions in address-driver circuits of a plasma-display panel (PDP) unit in which an energy-recovery scheme utilizing the resonance of a series-connected inductor and electrode parasitic capacitors is used. This is because an increase in parasitic capacitance and high-speed circuit operation become necessary as the display panel becomes larger in size and higher in resolution. In particular, low-power operation of address-driver ICs is key to avoiding the installation of heat sinks on the ICs. We propose herein new power-dispersion methods that can greatly reduce the power dissipation of address-driver ICs even when large parasitic capacitance is driven at high speed. The proposed methods enable a reduction in the power dissipation of address-driver ICs without deteriorating the operational speed by dispersing their powers into external resistors, and by supplying power to address-driver ICs in two voltage steps during both rising and falling time intervals when the address changes. Our results indicate that the power dissipation of address-driver ICs and the total cost of the address drive unit of a plasma-display panel can be reduced to 29% and 53%, respectively, compared with those of the ICs and the unit that are driven by the conventional address-driving method.