This paper tries to answer the following question: What type of support should be given to an automobile driver when it is determined, via some method to monitor the driver's behavior and the traffic environment, that the driver's intent may not be appropriate to a traffic condition? With a medium fidelity, moving-base driving simulator, three conditions were compared: (a) Warning type support in which an auditory warning is given to the driver to enhance his/her situation recognition, (b) action type support in which an autonomous safety control action is executed to avoid an accident, and (c) the baseline condition in which no driver support is given. Results were as follows: (1) Either type of driver support was effective in accident prevention. (2) Acceptance of driver support functions varied context dependently. (3) Participants accepted a system-initiated automation invocation as long as no automation surprises were possible to occur.

Apart from magnetic random access memories (MRAM), nonvolatile memories cannot be used without causing fatigue. As the use of MRAMs can solve fatigue problems, MRAMs have a large potential to open up large new markets. The manufacturing cost of LSIs cannot be reduced while they have not been produced massively. To increase the size of the MRAM market, new applications, in which MRAMs create added value, are needed. A demo system that models a drive recorder was developed to introduce the novel features of MRAMs, and a 4-Mb MRAM was developed to be used in the demo system.

Pole-tip-driven structure, which is composed of a coil wounded at the main pole tip, is favorable for obtaining a sharp and strong head field as a single-pole-type head. Three kinds of pole-tip-driven-type heads with different yoke and coil structures are investigated in terms of magnetomotive force dependence of head field and effect of coil recession. Field calculation by finite-element method (FEM) showed that the three heads exhibited the same field sensitivity in spite of the difference in distribution of coil exciting field and magnetization of the main pole. In a lower range of magnetomotive force the heads showed different dependence of field sensitivity on the coil recession. However, there was not much difference in degradation of sensitivity in a region near the saturation of field. Thus, the importance of reducing coil recession was confirmed as reported earlier.

In this paper, a new operational amplifier is presented that improves the specifications such as dc gain, common mode rejection ratio. To obtain these improvements, we have used the two important concepts of feedback and bulk amplification.

We present the 10-bit current driver LSI with 2-set current digital-to-analog converters (DACs) and output channel current sample and hold (S/H) circuits for large-size and high-resolution active matrix organic light emitting diode (AMOLED) display applications. This current driver LSI has 300 output channels and the output current ranges from 0 µA to 290 µA. The maximum output current level can be controlled by 2-bit control signals because the maximum output current level depends on display size and resolution. The chip was fabricated using 0.65µm BiCMOS process and characterized. The chip size is 16.8 mm3.6 mm. Experimental results show that the output current DNL is less than 0.4 LSB and that INL is less than 1.5 LSB. This is good enough to apply 15.5 inch WXGA (1280RGB768) AMOLED displays.

A DRAM-cell array with 12-F2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at 1 V and keeps the retention time of the single-cell array at 0.4 V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4 V.

This letter presents a novel implementation for Bus-Invert Coding called No Invert-Line Bus-Invert Coding (NIL-BIC) architecture. It not only removes the invert-lines used in previous BIC implementations, but sends the coding information without additional bus-transitions. NIL-BIC can save about 50% more bus-power than the implementations using invert-line.

A micromirror for an external cavity diode laser is described. The mirror is supported by two sets of parallel torsion bars enabling piston motion as well as rotation. These motions are for realizing continuous wavelength tuning. Adjusting two rotations electrically, the pivot of the mirror rotation can be controlled. The long stroke of the vertical comb is realized by the deep three-dimensional structure prepared by the wafer bending method.

In the design of an active matrix LCD (Liquid Crystal Display), the ratio of the pixel voltage to the video voltage (RPV) of a pixel is an important factor of the performance of the LCD, since the pixel voltage of each pixel determines its transmitted luminance. Thus, of practical importance is the issue of how to maintain the admissible allowance of RPV of each pixel within a prescribed narrow range. This constraint on RPV is analyzed in terms of circuit parameters associated with the sampling switch and sampling pulse of a column driver in the LCD. With the use of a minimal set of such circuit parameters, a design procedure is described dedicatedly for the sampling switch, which intends to seek an optimal sampling switch as well as an optimal sampling pulse waveform. A number of experimental results show that an optimal sampling switch attained by the proposed procedure yields a source driver with almost 18% less power consumption than the one by manual design. Moreover, the percentage of the RPVs within 1001% among 270 cases of fluctuations is 88.1% for the optimal sampling switch, but 46.7% for the manual design.

This letter proves the finish time predictability of EDZL (Earliest Deadline Zero Laxity) scheduling algorithm for multiprocessor real-time systems, which is a variant of EDF. Based on the results, it also shows that EDZL can successfully schedule any periodic task set if its total utilization is not greater than (m+1)/2, where m is the number of processors.

This paper describes a new low-power write driver circuit for mobile hard disk drive preamplifiers. To achieve low power consumption, we developed a write driver circuit with a single-stage MOS transistor as the current driver, which both switches and controls the write current. We also developed a reflection cancellation method to suppress the distortion of the write current waveform during write transition. Fabricated using 0.35-µm SOI-BiCMOS technology, this write driver circuit consumes low power, 380 mW (at 100 MHz).

To give comprehensive and consecutive understanding about load line regulation in the previous companion paper [1], more generalized expansion and theoretical derivation will be proposed in this paper. The paper provides an alternative current control approach to control the bias voltage compensation for full-color LED display based on the load-line approach. Modeling and formulation of the driver circuit system will be discussed in detail. Bias voltage compensation based on three load-lines regulation will keep the operating point fixed for the three color cells. Many properties can be observed based on the proposed model. Parasite effect such as the stray resistor and the stray capacitor will be considered in this paper. The associated standard RGB color testing for color cells and white color testing will be illustrated to verify the proposed compensation for the display driver circuit. The objectives of the luminance uniformity and the gray scale control can be achieved by using circuit approach. It is believed that this paper will be helpful to the driver circuit technology for the full-color LED display.

We present our recent results of the 10-bit data driver LSI for 42-inch diagonal TFT-LCD TV with full HD format. To develop data driver LSIs for a true 10-bit TFT-LCD TV with full HD (19201080) format, small chip area, low power consumption, and output uniformity between channels are key problems that must be solved. By applying a two-stage DAC which combines 8-bit resistor-string DAC and 2-bit binary weighted capacitor DAC, the area increase is limited to only 30% compared to the area of 8-bit resistor-string DAC. The output deviation between channels is successfully limited within 5 mV and the driver LSI with 414 outputs consumes the maximum total current of 16 mA when driving 42-inch HDTV panel. We confirmed that the picture with 10-bit shades of gray is much more natural than that with 8-bit shades of gray.

Bi-stable displays form the foundation of a novel and attractive LCD technology. From now on, images can be maintained on the LCD after driving voltages have been withdrawn from the electrodes. In low frame-rate applications such as e-books, e-labels, smartcards etc., this offers a major improvement in power consumption and battery life. However, bi-stable displays require high driving voltages and complex waveforms. Furthermore, the nature of some applications doesn't allow the use of relatively large passive components. This rules out more traditional approaches for high-voltage generation with external coils or capacitors. This paper describes the design of completely integrated and programmable high-voltage generators capable of generating output voltages up to 50 V out of a 3 V supply voltage. Features like 8-bit output voltage programmability and stabilisation were implemented to make this type of high-voltage generator suitable for bi-stable display drivers. Design aspects and simulation results are discussed, as well as measurements on prototype generators implemented in the 0.7 µm 100 V I2T100 technology from AMI Semiconductor.

To realize a secure networking infrastructure, the author is carrying out CUE (Coordinating Users' requirements and Engineering constraints) project with a network carrier and a VLSI manufacture. Since CUE-series data-driven processors developed in the project were specifically designed to be an embedded programmable component as well as a multi-processor element, particular design considerations were taken to achieve real-time multiprocessing capabilities essentially needed in multi-media communication environment. A novel data-driven paradigm is first introduced with special emphasis on VLSI-oriented parallel processing architectures. Data-driven protocol handlings on CUE-p and CUE-v1 are then discussed for their real-time multiprocessing capability without any runtime overheads. The emulation facility RESCUE (Real-time Execution System for CUE-series data-driven processors) was also built to develop scalable chip multi-processors in self-evolutional manner. Based on emulation results, the latest version named CUE-v2 was realized as a hybrid processor enabling simultaneous processing of data-driven and control-driven threads to achieve higher performance for inline processing and to avoid any bottlenecks in sequential parts of real-time programs frequently encountered in actual time-sensitive applications. Effectiveness of the data-driven chip multi-processor architecture will finally be addressed for lower power consumption and scalability to realize future VLSI processors in the sub-100 nm era.

This paper presents an improved gate drive circuit for high power GTO thyristors. The energy-storage/transfer characteristics of an air-core reactor and the fast switching characteristics of FET are employed to make a high gate current of sharp pulse form. The power loss in the gate drive circuit is reduced by using the low resistance and the hysteresis comparator to detect and control the steady on-gate current. The proposed gate drive circuit is analyzed and its usefulness is confirmed by experiments.

A method for fast but yet accurate performance evaluation of processor architecture is mostly desirable in modern processors design. This paper proposes one such method which can measure cycle counts and power consumption of pipelined processors. The method first develops a trace-driven performance simulation model and then employs simulation reuse in simulation of the model. The trace-driven performance modeling is for accuracy in which performance simulation uses the same execution traces as constructed in simulation for functional verification. Fast performance simulation can be achieved in a way that performance for each instruction in the traces is evaluated without evaluation of the instruction itself. Simulation reuse supports simulation speedup by elimination of an evaluation at the current state, which is identical to that at a previous state. The reuse approach is based on the property that application programs, especially multimedia applications, have many iterative loops in general. A performance simulator for pipeline architecture based on the proposed method has been developed through which greater speedup has been made compared with other approaches in performance evaluation.

Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becomes inadequate. In this paper, we present an efficient timing-driven global routing algorithm with buffer insertion. Our approach is capable of applying topological-based timing optimization and buffer insertion simultaneously with routablity considerations. Compared with previous works, we efficiently solve the timing issues under a limited buffer usage. The experimental results have demonstrated significant delay improvement within short runtime with very small number of buffers inserted.

The requirement for achieving the smoothness of mode transit between track seeking and track following has become a challenging issue for hard disk drive (HDD) motion control. In this paper, a random-optimization-based self-organizing neuro-fuzzy controller (RO-SNFC) for HDD servo system is presented. The proposed controller is composed of three designs. First, the concept of pseudo-errors is used to detect the potential dynamics of the unknown plant for rule extraction. Second, the propensity of the obtained pseudo-errors is specified by a cubic regression model, with which the cluster-based self-organization is implemented to generate clusters. The generated clusters are regarded as the antecedents of the T-S fuzzy "IF-THEN" rules. The initial knowledge base of the RO-SNFC is established. Third, the well-known random optimization (RO) algorithm is used to evolve the controller parameters for control efficiency and robustness. In this paper, a motion reference curve for HDD read/write head is employed. With the reference velocity curve, the RO-SNFC is used to achieve the optimal positioning control. From the illustrations, the feasibility of the proposed approach for HDD servo systems is demonstrated. Through the comparison to other approaches, the excellent performance by the proposed approach in access time and positioning smoothness is observed.

Limit cycle oscillations of rotor speed are substantially caused by inverter's dead time, when an induction motor (IM) drive operates in low frequency condition. In this paper, without any hardware modification, discontinuous PWM (DPWM3) modulate strategy possibly controls the unfavorable rotor speed limit cycle under no load operation condition. Simulated results are presented to demonstrate the effectiveness.