A sparse memory access architecture which is proposed to achieve a high-computational-speed neural-network LSI is described in detail. This architecture uses two key techniques, compressible synapse-weight neuron calculation and differential neuron operation, to reduce the number of accesses to synapse weight memories and the number of neuron calculations without incurring an accuracy penalty. The test chip based on this architecture has 96 parallel data-driven processing units and enough memory for 12,288 synapse weights. In a pattern recognition example, the number of memory accesses and neuron calculations was reduced to 0.87% that needed in the conventional method and the practical performance was 18 GCPS. The sparse memory access architecture is also effective when the synapse weights are stored in off-chip memory.

This paper describes the effectiveness of stream-oriented data-driven scheme for achieving autonomous fault management of hyper-distributed systems such as networks based on the Telecommunications Information Networking Architecture (TINA). TINA, whose specifications are in the finalizing phase within TINA-Consortium, is aiming at achieving interoperability and reusability of telecom applications software and independent of underlying technologies. However, to actually implement TINA network, it is essential to consider the technology constraints. Especially autonomous fault management at run-time is crucial for distributed network environment because centralized control using global information is very difficult. So far many works have been done on so-called off-line management but runtime management of service failure seems immature. This paper proposes introduction of stream-oriented data-driven processors to the autonomous fault management at runtime in TINA based distributed network environment. It examines the features of distributed network applications and technology requirements to achieve fault management of those distributed applications such as effective multiprocessing of surveillance, testing, reconfiguration in addition to ordinary processing.

A current controlled CMOS output driver was designed by using a temperature-insensitive reference current generator. It eliminates the need for overdesign of the driver transistor size to meet the delay specification at high temperature. Comparison with the conventional CMOS output driver with the same transistor size showed that the ground bounce noise was reduced by 2.5 times and the delay time was increased by 1.4 times, at 25 for 50pF load. The temperature variations of the DC pull-up and pull-down currents of the new output driver were 4% within the temperature range from -15 to 125 compared to the variations of 40 and 60% for pull-up and pull-down respectively for the conventional output driver. The temperature insensitivity of the reference current generator was achieved by multiplying two current components. one which is proportional to mobility and the other which is inversely proportional to mobility, by using a CMOS square root circuit. The temperature variation of the DC output current of the reference current generator alone was 0.77% within the entire temperature range from -15 to 125.

Circuit simulators are used to verify circuit functionality and to obtain detailed timing information before the expensive fabrication process takes place. They have become an essential CAD tool in an era of sub-micron technology. We have developed a new event-driven MOS circuit simulator to replace a direct method circuit simulator. In our simulator, partitioned subcircuits are analyzed by a direct method matrix solver, and these are controlled by an event-driven scheme to maintain accuracy. The key of this approach is how to manage events for circuit simulation. We introduced two types of events: self-control events for a subcircuit and prediction correcting events between subcircuits. They control simulation accuracy, and bring simulation efficiency through multi-rate behavior of a large scale circuit. The event-driven scheme also brings some useful functions which are not available from a direct method circuit simulator, such as a selected block simulation function and a batch simulation function for load variation. We simulated logic modules (buffer, adder, and counter) with about 1000 MOSFETs with our event-driven MOS circuit simulator. Our simulator was 5-7 times faster than a SPICE-like circuit simulator, while maintaining the less than 1% error accuracy. The selected block simulation function enables to shorten simulation time without losing any accuracy by selecting valid blocks in a circuit to simulate specified node waveforms. Using this function, the logic modules were simulated 13-28 times faster than the SPICE-like circuit simulator while maintaining the same accuracy.

A vertical magnetoresistive (MR)/inductive head using the current bias technique has been developed for high-density magnetic recording. In this head, the sense current is orthogonal to the air-bearing surface (ABS). The area exposed at the ABS of the MR element is beneath the front lead, and the active area of the sensor is positioned behind that area. The MR element is composed of two permalloy films separated by a thin nonmagnetic material. The easy axis of the films is oriented parallel to the ABS and the films are magnetostatically coupled. The magnetic field created by the sense current is applied in the direction of the easy axis and the MR element is stabilized. In this head structure, no MR-element-stabilizing layer, such as an antiferromagnetic film or a hard magnetic film, is needed. Since the permalloy film beneath the front lead acts as a front flux guide, the signal flux propagates in the sensing area of the MR element behind the ABS. The new vertical MR head has the same electrical performance characteristics as the conventional horizontal MR head. The offtrack signal profile is symmetric against the track center because the magnetization of the two permalloy films rotates symmetrically in the signal-flux direction. The output signal level of this head is independent of the read trackwidth, which favors a narrow trackwidth. The exposed portion at the ABS is only connected to the common lead and is at ground potential. In this design, electrostatic breakdown does not occur and no corrosion is observed. Tests have shown that as the flying height is reduced, the error rate is reduced and noise does not increase. This head structure appears suitable for the near-contact recording of the near future.

This paper describes a simulation technique of start-up characteristics that considers a nonlinearity of the drive level of quartz crystal resonators. A nonlinear resonator model for SPICE where the resonant resistance varies with the voltage added to a resonator is proposed. In an examination using a transistor Colpitts oscillator, the simulation using this technique agreed with the experimental results very well.

A 10-kW (53V/200A), forced-air-cooled DC-DC converter has been developed for fuel cell systems. This converter uses new high-voltage bipolar-mode static induction transistors (BSIT), a new driving method, a zero-voltage-switched pulse-width-modulation technique, and a new litz wire with low AC resistance. It weighs only 16.5kg, has a volume of 26,000cm3, operates at 40kHz, and has a power conversion efficiency of about 95%. The power loss of this converter is 20% less than that of conventional natural-air-cooled DC-DC converters, and the power density is 3 times as high.

This paper describes an efficient slew rate enhancement technique especially suitable for an operational amplifier used in an LCD driver IC. This technique employs an input-dependent biasing without directly monitoring an input; instead, monitoring an output of the first stage of the amplifier. This enhancement technique is easily applied to a conventional two-stage operational amplifier and requires only 8 additional transistors to increase slew rates for both rising and falling edges. The bias currents of the first and the second stages are simultaneously controlled by this biasing. Experimental operational amplifiers with and without this enhancement have been fabricated to demonstrate the improvement of slew rate. Slew rates of 12.5V/µsec for the rising edge and 50V/µsec for the falling edge with a 100 pF load capacitance have been achieved by this technique, compared with slew rates of 0.3V/µsec for the rising edge and 5V/µsec for the falling edge in the conventional amplifier.

A timing-driven global routing algorithm is proposed that directly models the path-based timing constraints. By keeping track of the critical path delay and channel densities, and using novel heuristic criteria, it can select routing paths that minimize area as well as satisfy the timing constraints. Using bipolar-specific features, this router can be used to design LSI chips that handle signals with speeds greater that a gigabit per second. Experimental results shows an average delay improvement of 17.6%.

A polarity-convertible driver is necessary as a basic component of several Josephson random access memories. This driver must be able to inject a current having positive or negative polarity into a load transmission line such as a word or bit line of the RAM. In this paper, we propose a resistor coupled Josephson polarity-convertible driver which is highly sensitive to input signals and has a wide operating margin. The driver consists of several Josephson junctions and several resistors. The input signal is directly injected to the driver through the resistors. The circuit design is discussed on the operating principle of the driver. The driver is fabricated by 1.5 µm Nb technology with Nb/AlOx/Nb Josephson junctions, two layer Nb wirings, an Nb ground plane, Mo resistors, and SiO2 insulators. The Nb/AlOx/Nb Josephson junctions are fabricated using technology refined for sub-micron size junctions. The insulators between wirings are formed using bias sputtering technique to obtain good step coverage. The driver circuit size is 53 µm34 µm. Measurements are carried out at 10 kHz to quasistatically test the polarity-convertible function and the operating margin of the driver. Proper polarity-convertible operation is confirmed for a large operating bias margin of 70% at a fairly small input current of 0.3 mA.

The data-driven model of computation is well suited for flexible and highly parallel simulation of neural networks. First, the operational semantics of data-driven languages preserve the locality and functionality of neural networks, and naturally describe their inherent parallelism. Second, the asynchronous data-driven execution facilitates the implementation of large and scalable multiprocessor systems, which are necessary to obtain considerable degrees of simulation sppedups. In this paper, we present a dynamic data-driven multiprocessor system, and demonstrate its suitability for the paralel simulation of back propagation neural networks. Two parallel implementations are described and evaluated using an image data compression network. The system is scalable, and as a result, the performance improved proportionally with the increase in number of processors.

This paper describes a segment driver IC for high-quality liquid-crystal-displays (LCDs). Major design issues in the segment driver IC are a wide signal bandwidth and excessive output-offset variation both within a chip and between chips. After clarifying the trade-off relation between the signal bandwidth and the output-offset variation originated from conventional sample-and-hold (S/H) circuits, two wide-band S/H circuits with low output-offset variation have been introduced. The basic ideas for the proposed S/H circuits are to improve timing of the sampling pulses applied to MOS analog switches and to prevent channel charge injection onto a storage capacitor when the switches turn off. The inter-chip offset-cancellation technique has been also introduced by using an additional S/H circuit. Two test chips were implemented using the above S/H circuits for demonstration purposes. The intra-chip output-offset standard deviation of 9.5 mVrms with a 3dB bandwidth of 50 MHz was achieved. The inter-chip output-offset standard deviation was reduced to 5.1 mVrms by using the inter-chip offset-cancellation technique. The evaluation of picture quality of an LCD using the chips shows the applicability of the proposed approaches to displays used for multimedia applications.

This paper discusses the design of an ITS to realize a load-oriented tutoring to enhance the student's explanation understanding. In the explanation understanding, it is to be hoped that a student not only memorizes the new information from an explanation, but also relates the acquired information with his/her own knowledge to recognize what it means. This relating process can be viewed as the one in which the student structures his/her knowledge with the explanation. In our ITS, we regard the knowledge-structuring activities as the explanation understanding. In this paper, we propose an explanation, called a load-oriented explanation, with the intention of applying a load to the student's knowledge-structuring activities purposefully. If the proper load is applied, the explanation can induce the student to think by himself/herself. Therefore he/she will have a chance of gaining the deeper understanding. The important point toward the load-oriented explanation generation is to control the load heaviness appropriately, which a student will bear in understanding the explanation. This requires to estimate how an explanation promotes the understanding activities and how much the load is applied to the activities. In order to provide ITS with the estimation, we have built an Explanation Effect Model, EEM for short. Our ITS consists of an explanation planner and a self-explanation environment. The planner generates the load-oriented explanation based on EEM. The system also makes a student explain the explanation understanding process to himself/herself. Such self-explanation is useful to let the student be conscious of the necessity of structuring his/her knowledge with the explanation. The self-explanation environment supports the student's self-explanation. Furthermore, if the student reaches an impasse in self-explaining, the planner can generate the supporting explanation for the impasse.

Automotive electronics technology has become extremely advanced in the regions of automotive engine control, anti-skid brake control, and others. These control systems require highly advanced control performance and high speed microprocessors which can rapidly execute interrupt processing. Automotive engine control systems are now widely utilized in cars with high speed, high power engines. At present, it is generally acknowledged that such high performance engine control for the 10,000 rpm, 12 cylinder engines requires three or more conventional microprocessors. We fabricated an engine control system prototype incorporating the data-driven processor under development, which was installed in an actual automobile. In this paper, the characteristics of the engine control program and simulation results are firstly discussed. Secondly, the structure of the engine control system prototype and the control performance applied to the actual automobile are shown. Finally, from the results of software simulation and the installation of the engine control system prototype with the data-driven processor, we conclude that a single chip data-driven microprocessor can control a high speed, high power, 10,000 rpm, 12 cylinder automobile engine.

High speed simulation of neural networks can be achieved through parallel implementations capable of exploiting their massive inherent parallelism. In this paper, we show how this inherent parallelism can be effectively exploited on parallel data-driven systems. By using these systems, the asynchronous parallelism of neural networks can be naturally specified by the functional data-driven programs, and maximally exploited by pipelined and scalable data-driven processors. We shall demonstrate the suitability of data-driven systems for the parallel simulation of neural networks through a parallel implementation of the widely used back propagation networks. The implementation is based on the exploitation of the network and training set parallelisms inherent in these networks, and is evaluated using an image data compression network.

We propose a continuous speech recognition algorithm utilizing island-driven A* search. Conventional left-to-right A* search is probable to lose the optimal solution from a finite stack if some obscurities appear at the start of an input speech. Proposed island-driven A* search proceeds searching forward and backward from the clearest part of an input speech, and thus can avoid to lose the optimal solution from a finite stack.

Recessed-gate DMTs (doped-channel hetero-MISFETs) with i-AlGaAs/n-GaAs structure and pseudomorphic i-AlGaAs/n-InGaAs/i-GaAs structure have been developed. Broad plateaus in gm and fT provide evidence that the DMTs make the devices suitable for high-speed large-signal operation. GaAs DMTs with 0.35 µm-length have gate turn on voltage of 0.7 V, maximum transconductance of 320 mS/mm and fT of 41 GHz. Pseudomorphic DMTs have gate turn on voltage of 0.9 V, maximum transconductance of 320 mS/mm, fT of 42 GHz and have the enhanced advantages of high current drivability and large gate swing. Further more, with the use of the recessed-gate DMTs, a high-speed laser driver IC for multi-Gb/s optical communication systems are demonstrated. This laser driver IC operates at 10 Gb/s with rise and fall times as fast as 40 psec, and it can drive up to 60 mA into a 25 Ω load.

A feed-forward (FF) BiNMOS driver that combines a multi-stage CMOS inverter and a bipolar emitter-follower transistor is proposed as a low-voltage BiCMOS driver. High-speed and low-voltage operation is made possible by a multi-stage inverter and feed-forward control from the pre-stage inverters to the bipolar emitter-follower. Two key factors determining the driver delay time, output load capacitance and wiring resistance, are described and analyzed in detail. Experiments with a gate-chains test chip fabricated with 0.5-µm BiCMOS technology confirm the low-voltage operation of the FF-BiNMOS driver. Applications of the new driver to a BiCMOS SRAM are also described.

We have successfully developed an optical receiver and a laser driver circuit which were implemented with 0.35 µm GaAs JFETs (junction Field Effect Transistors). The 0.35 µm GaAs. JFET had the typical transconductance of 480 mS/mm with small drain conductance. An interdigit MSM (Metal Semiconductor Metal) -type photodetector and the JFETs were monolithically integrated on a GaAs substrate for the optical receiver. The fabricated optical receiver demonstrated Gb/s operation with a very low power consumption of 8.2 mW. The laser driver circuit operated at up to 4.0 Gb/s.

A new algorithm for timing driven placement based on the fuzzy theory is proposed. In this method, the signal delay on the longest path, the chip area and the total wire length can be simultaneously minimized. Introducing the probability measures of fuzzy events, falling down into the local optimal solutions can be avoided. At first, we define the fuzzy placement relation using the graph distance matrix and fuzzy distance relation matrix, and we give a new placement method based on the fuzzy placement relation and the probability measures of fuzzy events. Secondly, we extend this placement method so as to apply to the timing driven placement problem by introducing a fuzzy membership functions which represent the signal delay on the longest path and the chip area. Finally, experimental results are shown to compare our method with one of the previous methods.