A wireless communications system with a transmission speed of 18 Mbit/s is presented using the 2.4 GHz ISM band. This system employs the Carrier Frequency Offset-Spread Spectrum (CFO-SS) scheme and the Dual-Polarization Staggered Transmission (DPST) scheme. The 18 Mbit/s CFO-SS system (named CFO-SS18) was developed and its performance evaluated in fields. In this paper, the detailed operating principle of CFO-SS and DPST schemes, together with the specifications and structures of CFO-SS18, are presented. Results of indoor and field tests obtained by using CFO-SS18 are also presented.

A novel technique for automatic segmentation of a brain region in single channel MR images for visualization and analysis of a human brain is presented. The method generates a volume of brain masks by automatic thresholding using a dual curve fitting technique and by 3D morphological operations. The dual curve fitting can reduce an error in curve fitting to the histogram of MR images. The 3D morphological operations, including erosion, labeling of connected-components, max-feature operation, and dilation, are applied to the cubic volume of masks reconstructed from the thresholded brain masks. This method can automatically segment a brain region in any displayed type of sequences, including extreme slices, of SPGR, T1-, T2-, and PD-weighted MR image data sets which are not required to contain the entire brain. In the experiments, the algorithm was applied to 20 sets of MR images and showed over 0.97 of similarity index in comparison with manual drawing.

In this paper, we introduce a concept of minimum bandwidth guaranteed service model for mobile multimedia. In this service model, service is defined in the context of the guaranteed minimum bandwidth and the residual service share. Each flow under this service model is guaranteed with its minimum bandwidth and provided with more in proportion to the residual service share if there is leftover bandwidth. The guaranteed minimum bandwidth assures a flow to keep minimum tolerable quality regardless of the network load, while the leftover bandwidth enhances the quality of service according to the application's adaptivity and the user's interest. We show that the minimum bandwidth guaranteed service model could be implemented by a two-folded wireless packet scheduler consisting of a guaranteed scheduler and a sharing scheduler. Wireless channel condition of each flow is considered in scheduling so that wireless resource can be distributed only to the flows of good channel state, improving total wireless link utilization. We evaluate the service model and the scheduling method by simulation and implementation.

Dual-Banyan is a buffered banyan asynchronous transfer mode (ATM) switch encompassing bifurcated queueing as its buffering strategy. This paper describes an efficient analytical model, based on iterative calculations, for performance evaluation of the Dual-Banyan switch under uniform and non-uniform traffic patterns with much less time than the simulation. The efficiency of the given model is verified through a comparison with simulation results. Another benefit of our model is the possibility to adopt it in any non-uniform incoming traffic. At last, we compare performance of Dual-Banyan switch and Input Buffer Banyan, and show that Dual-Banyan switch has significant better performance levels.

This paper presents effective methods to calculate dual frame of the short-time Fourier expansion (STFE) in l2(Z). Based on a relationship between the prototype window used for generating a frame and the dual prototype window used for generating a dual frame in the STFE, two useful numerical methods with a finite frame operator are proposed to obtain finite support dual frames in time domain formulation. The methods can be used to construct the multiple STFE (MSTFE) suitable for a time-frequency analysis, synthesis and coding of discrete-time nonstationary signals. Numerical simulation results are given to verify the effectiveness of the calculation of dual frame.

We developed a method for analysis of boron penetration and gate depletion using N+ and P+ dual-gate PMOSFETs. An N+ gate PMOSFETs, which is immune to boron penetration and gate depletion, exhibited the threshold voltage shifts and fluctuation in P+ gate PMOSFETs fabricated using identical N- substrates. We showed the importance of Vth fluctuation analysis and found that the Vth fluctuation in N+ gate PMOSFETs was negligible, but, the Vth fluctuation in P+ gate PMOSFETs was significant, indicating that the Vth fluctuation in P+ gate PMOSFETs was dominated by boron penetration. It was also shown, for the first time, that boron penetration occurred with gate depletion, and gate depletion must be very strong to suppress boron penetration. The dual-gate PMOSFET method makes it possible to select high-performance G-bit DRAM fabrication processes that are robust against Vth fluctuation.

In this paper, we consider a network design problem with hub-and-spoke structure. We propose a relaxation technique for the problem where the location of hub nodes is given and decides the allocation of non-hub nodes to one of the hub nodes. We linearize the non-convex quadratic objective function of the original problem, introducing Hitchcock transportation problems defined for each pair of non-hub nodes. We provide two linear relaxation problems, one based on the Hitchcock transportation problems and the other on the dual Hitchcock transportation problems. We show the tightness of the lower bounds obtained by our formulations by computational experiences.

Two novel linearization processes in electro-absorption-modulator (EAM) are proposed and demonstrated. These two modulation schemes are used to compensate the nonlinear component of the EAM by controlling the DC bias voltages of the each EAM separately. The simulations on the nonlinearity of EAM and linearization process are performed in both time and frequency domains. From a serially cascaded modulation simulation, a reduction of 16 dB in IMD3, 45 dB in IMD5 and the following increase of 15 dB in linear dynamic rage (LDR) are achieved. In dual-parallel modulation experiment at 8 GHz, a reduction of 23 dB in IMD3 and the following increase of 15.1 dB in LDR of are achieved compared to those of a single EAM operation.

The jitter characteristics of synchronous residual time stamp (SRTS) method used in ATM adaptation layer type 1 (AAL1) are analyzed. In this letter, the root mean square amplitude of filtered SRTS jitter is calculated and the computer simulation has been carried out to show jitter of SRTS method considering also the phase time error of network clocks.

Y. S. Han et al. have proposed an efficient maximum likelihood decoding (MLD) algorithm using A* algorithm which is the graph search method. In this paper, we propose a new MLD algorithm for linear block codes. The MLD algorithm proposed in this paper improves that given by Han et al. utilizing codewords of dual codes. This scheme reduces the number of generated codewords in the MLD algorithm. We show that the complexity of the proposed decoding algorithm is reduced compared to that given by Han et al. without increasing the probability of decoding error.

The international telecommunication standards bodies such as ITU-T, ATM Forum, and IETF recommend the dual leaky bucket for the traffic specifications for VBR service. On the other hand, recent studies have demonstrated multiple time-scale burstiness in compressed video traffic. In order to fill this gap between the current standards and real traffic characteristics, we present a standard-compatible traffic parameter selection method based on the notion of a critical time scale (CTS). The defined algorithm is optimal in the sense that it minimizes the required amount of link capacity for a traffic flow under a maximum delay constraint. Simulation results with compressed video traces demonstrate the efficiency of the defined traffic parameter selection algorithm in resource allocation.

Wavelet based image compression is getting popular due to its promising compaction properties at low bitrate. Zerotree wavelet image coding scheme efficiently exploits multi-level redundancy present in transformed data to minimize coding bits. In this paper, a new technique is proposed to achieve high compression by adding new zerotree and significant symbols to original EZW coder. Contrary to four symbols present in basic EZW scheme, the modified algorithm uses eight symbols to generate fewer bits for a given data. Subordinate pass of EZW is eliminated and replaced with fixed residual value transmission for easy implementation. This modification simplifies the coding technique as well and speeds up the process, retaining the property of embeddedness.

The heterogeneous autonomous decentralized system technology offers a way to integrate different types of context-related autonomous decentralized (sub) systems into a coherent system. The aim of this research is to model and evaluate the communication capacity among the subsystems connected by communication gateways of a heterogeneous autonomous decentralized system. Failures of subsystems and communication gateways in the system are taken into account. We use graphs to represent the topologies of heterogeneous autonomous decentralized systems and use the residual connectedness reliability (RCR) to characterize the communication capacity among its subsystems connected by its gateways. This model enables us to share research results obtained in residual connectedness reliability study in graph theory. Not to our surprise, we learnt soon that computing RCR of general graphs is NP-hard. But to our surprise, there exist no efficient approximation algorithms that can give a good estimation of RCR for an arbitrary graph when both vertices and edges may fail. We proposed in this paper a simulation scheme that gave us good results for small to large graphs but failed for very large graphs. Then we applied a theoretical bounding approach. We obtained expressions for upper and lower bounds of RCR for arbitrary graphs. Both upper and lower bound expressions can be computed in polynomial time. We applied these expressions to several typical graphs and showed that the differences between the upper and lower bounds tend to zero as the sizes of graphs tend to infinite. The contributions of this research are twofold, we find an efficient way to model and evaluate the communication capacity of heterogeneous autonomous decentralized systems; we contribute an efficient algorithm to estimate RCR in general graph theory.

Dual FDTS/DF detector is an advanced version of FDTS/DF detector that gives significant performance improvement over FDTS/DF scheme on linear channels, and moreover, in contrast to other dual-detector schemes, it is suitable for various d-constraint coded channels. As recording density increases, channel nonlinearities such as non-linear transition shift (NLTS) and partial erasure (PE) degrade the performance of detectors. In this paper, we use nonlinear channel models to study the BER performance of dual FDTS/DF detector and compare the performances with those of other detectors through bit-by-bit simulations. Simulation results show that the dual FDTS/DF detector is superior in performance compared to FDTS/DF and MDFE detectors even on nonlinear channels, and it gives comparable BER performance with M2DFE (adv.) on nonlinear channels. Results also indicate that the detectors on the d=1 coded channels are more robust to channel nonlinearities compared to those of other detectors (such as PRML family detectors) on the d=0 coded channels.

In this paper, a novel three-port antenna structure, named 180 antenna hybrid, is proposed and demonstrated. This structure is composed of a Wilkinson power divider with the isolation resistor replaced by an aperture-coupled patch antenna. The equivalent series impedance of the antenna can be adjusted to the required one by properly choosing the dimensions of the patch and the coupling aperture. When a signal is fed to the balanced port of this antenna hybrid, the power is equally split, with equal phases, to the two unbalanced ports. No power is radiated out from the antenna. In the other hand, a signal received from the antenna will be split with equal power but 180 phase difference to the two unbalanced ports. The balanced port is an isolation port. The measurement results showed good agreement with the characteristics to be designed. Three applications of this 180 antenna hybrid are introduced, that is, a balanced mixer, an active transmitting antenna, and a dual-radiation-mode antenna array. The balanced mixer was constructed with diodes directly mounted on the two unbalanced ports of the antenna hybrid. The LO signal is fed from the balanced port and RF signal is received from the antenna. The active transmitting antenna was implemented with feedback configuration. The route from one of the unbalanced port to the balanced port of the antenna hybrid was used as the feedback path. A locking signal may be injected from the other unbalanced port. Finally, through a three-quarter-wavelength microstrip line, the balanced port of the antenna hybrid was connected to another aperture-coupled patch antenna to form a dual-radiation-mode antenna array. The in-phase and out-of-phase radiation patterns of this two-element array can be obtained from two unbalanced ports of the antenna hybrid, respectively.

Personal identity verification has a great variety of applications including access to computer terminals, buildings, credit card verification as well as EC. Algorithms for personal identity verification can be roughly classified into four categories depending on static/dynamic and biometric/physical or knowledge based. Finger prints, iris, retina, DNA, face, blood vessels, for instance, are static and biometric. Algorithms which are biometric and dynamic include lip movements, body movements and on-line signatures. Schemes which use passwords are static and knowledge based, whereas methods using magnetic cards and IC cards are physical. Each scheme naturally has its own advantages and disadvantages. A new algorithm is proposed for pen-input on-line signature verification incorporating pen-position, pen-pressure and pen-inclinations trajectories. A preliminary experiment is performed on a data base consisting of 293 genuine writings and 540 forgery writings, from 8 individuals. Average correct verification rate was 97.6% whereas average forgery refection rate was 98.7%. Since no fine tuning was done, this preliminary result looks very promising.

In this paper, we propose a fine grain Cooled Logic architecture for low-power oriented processors. Cooled Logic detects, in novel hardware method with dual-rail logic, functional blocks to be active, and stops clocks to each of the functional blocks in order to make it inactive at certain periods. To confirm the effectiveness of our approach, we design a 4-bit and a 16-bit event-driven array multipliers, and analyze their power consumption by the HSPICE simulator. As a result, it is shown that Cooled Logic has a tendency to reduce power consumptions in both the functional blocks and the clock drivers of the multipliers.

Research on the propagation characteristics in the microwave band aiming at broadband mobile services is attracting much attention. Typical examples are the Unlicensed-NII (U-NII) band in the U.S. and HIPER-LAN band in Europe, i.e. 5.2 GHz. An efficient approach to revealing the propagation characteristics in the 5-GHz band is to utilize the existing propagation data accumulated by many researchers on the 2-GHz band. This paper presents the differences in path loss between the 5.2-GHz and 2.2-GHz bands in a residential area by using a 5.2-GHz/2.2-GHz dual band antenna. This antenna enables a direct comparison of 5.2 GHz and 2.2 GHz in terms of the propagation characteristics. We found that the difference in path loss between the 2.2-GHz and 5.2-GHz bands depends on only the base/mobile station antenna height. Based on this, we formulate the relationship between the heights of the base/mobile station antennas and the difference in path loss between the 2.2-GHz and 5.2-GHz bands.

This paper proposes two novel Multi-bit Delta-Sigma Modulator (Δ Σ M) architectures based on a Dual-Quantization architecture. By using multi-bit quantization with single-bit feedback, Both eliminate the need for a multi-bit digital-to-analog converter (DAC) in the feedback loop. The first is a Digital quantization-Error Canceling Multi-bit (DECM)-Δ Σ M architecture that is able to achieve high resolution at a low oversampling ratio (OSR) because, by adjusting the coefficients of both analog and digital circuits, it is able to cancel completely the quantization error injected into the single-bit quantizer. Simulation results show that a signal-to-quantization-noise ratio of 90 dB is obtained with 3rd order 5-bit quantization DECM-Δ Σ M at an OSR of 32. The second architecture, an analog-to-digital mixed (ADM)-Δ Σ M architecture, uses digital integrators in place of the analog integrator circuits used in the Δ Σ M. This architecture reduces both die area and power dissipation. We estimate that a (2+2)-th order ADM-Δ Σ M with two analog-integrators and two digital-integrators will reduce the area of a 4-th order Δ Σ M by 15%.

This paper reviews the recent development of the Boolean Single Flux Quantum (BSFQ) circuits. BSFQ circuits perform Boolean operation based on the superconducting flux level, and let digital bits propagate in the form of 'set' and 'reset' pulses using dual-rail Josephson transmission line (JTL). Just the same as CMOS circuits BSFQ circuits do not require any local clock system for the operation gates, and thus are delay insensitive, and comparably simple in terms of the number of Josephson junctions. Implementation of basic BSFQ circuits, namely 'NOT,' 'AND,' 'OR,' 'XOR' gate, is described. These circuits have been experimentally tested, and their workability has been proven.