A RF front-end chip for a dual-band Global Positioning System (GPS) receiver for L1 and L2 bands is designed using 0.25 µm CMOS technology. All function blocks of the GPS front-end are integrated onto one chip. The low noise amplifier has input matching over a wide frequency range to handle the L1 and L2 bands. This receiver uses a dual-band image-reject mixer with the quadrature mixer sharing a transconductor stage. This configuration enables the RF blocks to be shared with the L1 and L2 bands. The receiver has a chip area of 3.16 mm3.16 mm, and consumes 35 mA at 2.5 V.

An asymmetric Dual Metal Stack Gate (DMSG) SOI MOSFET transistor has been investigated for its enhanced electrical characteristics. A 2-D physical model has been proposed and its results have been confirmed by those obtained by simulation. These results predict better short channel effects such as drain induced barrier lowering (DIBL) characteristics and hot carrier effects for this device compared to those for conventional SOI MOSFETs. The effects of the Stacked Gate (SG) and Dual Metal Gate (DMG) structures on short channel effects are compared. It has been observed that SG reduces DIBL significantly, while DMG prevents the normal roll-off of the threshold voltage reduction.

In this paper, a detailed model of a hybrid dual-stage Raman/erbium-doped fiber (EDF) amplifier is presented. This model takes into account the impact of double Rayleigh backscattering (DRB) noise, amplified spontaneous emission (ASE) noise and Kerr-nonlinearity induced impairments in the amplification process. Using this model, we present a comprehensive analysis of the operation of hybrid dual-stage Raman/EDF amplifiers under above impairments. We show that under fixed total gain conditions for the amplifier module, high Raman gain causes the introduction of increased DRB noise to the amplified signals whereas low Raman gain causes the introduction of high ASE noise power through EDF amplifier. Therefore a balance between the Raman amplifier gain and EDF amplifier gain is required for optimal operation. These observations are then combined to show an optimization process, which could be applied to improve the design of hybrid dual-stage Raman/EDF amplifiers.

One of the remaining issues of Mobile IP is a mobile host (MH) needs to update its location each time it moves from one subnet to another, even when it is in dormant mode while roaming. This practice is apparently not efficient in terms of location update cost and power consumption. Recent research works have attempted to address that problem by extending Mobile IP with a layer 3 paging mechanism so-called IP paging. Particularly, IP Individual Paging schemes, which are customized to each MH, have attracted considerable interest of researchers. The employment of adaptability in some manner to MH parameters in order to enhance the efficiency of IP paging schemes is probably a promising approach. In this paper, we present an analysis on the effects of both host-adaptability and time-adaptability to MH parameters in Individual Paging schemes by comparing the signaling cost of an adaptive Individual Paging scheme to that of a non-adaptive counterpart. From our analysis, specifying the optimal paging area (PA) is critical in saving signaling cost of IP paging. Thus, our investigation is focused on the adaptability of PA to maintain its optimality.

In this paper, a dual level access scheme is proposed to provide two levels of access to the broadcast data; one to video signals protected for authorized users, another to extra information e.g. advertisements provided for the remaining users in the network. In the scheme, video signals in MPEG format are considered. The video contents are protected from unauthorized viewing by encrypting the DC coefficients of the luminance component in I-frames, which are extracted from the MPEG bit-stream. An improved direct sequence spread spectrum technique is used to add extra information to non-zero AC coefficients, extracted from the same MPEG bit-stream. The resultant MPEG bit-stream still occupies the same existing bandwidth allocated for a broadcast channel. At the receiver, the extra information is recovered and subtracted from the altered AC coefficients. The result is then combined with the decrypted DC coefficients to restore the original MPEG bit-stream. The experimental results show that less than 2.9% of the size of MPEG bit-stream was required to be encrypted in order to efficiently reduce its commercial value. Also, on average, with a 1.125 Mbps MPEG bit-stream, an amount of extra information up to 1.4 kbps could be successfully transmitted, while the video quality (PSNR) was unnoticeably degraded by 2.81 dB.

Power consumption is a major concern in embedded microprocessors design. Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speed-critical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power. We evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is substantially energy-efficient while it suffers performance degradation.

In this paper, we propose a new feature extraction method that combines both HMT-based denoising and weighted filter bank analysis for robust speech recognition. The proposed method is made up of two stages in cascade. The first stage is denoising process based on the wavelet domain Hidden Markov Tree model, and the second one is the filter bank analysis with weighting coefficients obtained from the residual noise in the first stage. To evaluate performance of the proposed method, recognition experiments were carried out for additive white Gaussian and pink noise with signal-to-noise ratio from 25 dB to 0 dB. Experiment results demonstrate the superiority of the proposed method to the conventional ones.

The ring Fp + uFp + + uk-1Fp may be of interest in coding theory, which have already been used in the construction of optimal frequency-hopping sequence. In this work, cyclic codes over Fp + uFp + + uk-1Fp which is an open problem posed in [1] are considered. Namely, the structure of cyclic code over Fp + uFp + + uk-1Fp and that of their duals are derived.

Projection-based model reductions become a necessity for efficient interconnect modeling and simulations. In order to choose the order of the reduced system that can really reflect the essential dynamics of the original interconnect, the residual error of the transfer function can be considered as a stopping criteria to terminate the Arnoldi iteration process. Analytical expressions of this residual error are derived in detail. Furthermore, it can be found that the approximate transfer function can also be expressed as the original interconnect model with some additive perturbations. The perturbation matrix only involves resultant vectors at the previous step of the Arnoldi algorithm. These error information will provide a guideline for the order selection scheme used in the Krylov subspace model-order algorithm.

The paper first researches the properties of neural networks in the framework of the dual linear programming theory, then discusses the variation range of a Hessian matrix associated to dual linear programming problems. By means of eigenvalues method, a Lipschitz constant based formula for determining the algorithm step-size is presented. Two examples are given to show that the proposed formula is efficacious.

The investigation presents a low cost and low insertion loss X-band dual mode bandpass filter (BPF) based on inexpensive commercial FR4 substrate. The proposed filter at a central frequency f0 of 11.3 GHz has high filter performance filter with a fractional bandwidth of 14%, the insertion loss of -2.7 dB, and two transmission zeros. The designed procedures are presented in this letter and the fabricated filter verifies the proposed designed concept.

The paper reports a compact and high performance dual-band bandpass filter (BPF) using two types of dual-mode resonators. The dual mode cross shaped resonator and the three dual mode ring resonators in the designed dual-band BPF are excited to control the first and second passband, respectively. It is shown that the designed and fabricated dual-band BPF has narrow bandwidths and very sharp attenuation rate due to the existence of the transmission zeros. The frequency response of the designed dual-band BPF shows good agreement between the simulations and experiments.

This paper presents a computer-aided design procedure of simulated annealing algorithm to optimize dual-wideband microstrip line filters with symmetrical at least 500 MHz bandwidths respectively. This method demonstrates the superiority of designing microstrip line dual-band filters. The value of characteristic impedances and electrical lengths of transmission lines synthesizing 2.4 GHz and 5.2 GHz dualband filters with a single input and a single output are adjusted to the annealing process by the optimization algorithm. The fabricated dual-wideband spectral transmittance and reflectance curves of these filters applying this method all effectively achieved desired high performances and resulted in a lower cost dual-band filters and open the way to commercial mass production. The method is applicable not only in 2.4 GHz and 5.2 GHz, but can be applied to any other multi-frequency bands.

This paper proposes a novel dual-mode ring bandpass filter (BPF) using defect ground structure (DGS). The proposed filter provides wide stopband characteristic resulted from the bandgap characteristic of DGS for suppressing spurious response of the dual-mode ring BPF. The H shaped DGS cell is modeled as a parallel LC resonator and the equivalent circuit parameters are extracted. The relationship between bandgap characteristic and design parameters of DGS dimension is discussed and the bandgap characteristic of DGS on the filter performance is also investigated. The novel proposed filter has the frequency characteristics with a central frequency f0 = 7.7 GHz, a 3-dB bandwidth of 4.5% and wider stopband from 9 to 15.5 GHz at the level of -35 GHz. Measured results of experimental filter has good agreement with the theoretical simulation results.

This paper presents a dual-frequency microstrip antenna for both 2 GHz and 5 GHz for a dual-band receiver. For a simple structure and low cost design, the microstrip feed circuit is designed on the same substrate as the antenna elements. Each antenna element is directly fed by the microstrip line, and the open stubs are loaded on the feed line of 2 GHz to suppress the higher order mode resonances between 2 GHz and 5 GHz. The feed line length of each antenna is adjusted so as to change it to the open condition at the other element frequency at the feed point. In addition, we propose the antenna structure in which two antenna elements for 2 GHz are split and placed at either sides of the 5 GHz antenna to coincide with the center positions of each antenna element. We investigate the proposed antenna by calculations and measurements to show the combiner free design for the dual band antenna.

This paper presents a novel layout approach using dual supply voltage technique. In Placing and Routing (P&R) phase, conventional approaches for dual supply voltages need to separate low supply voltage cells from high voltage ones. Consequently its layout tends to be complex compared with single supply voltage layout. Our layout approach uses cells having two supply voltage rails. Making these cells is difficult in bulk due to increase in area by n-well isolation or in delay by negative body bias caused by sharing n-well. On the other hand, making cells with two supply voltage rails is easy in body-tied PD-SOI owing to trench isolation of each body of transistor. Since our approach for dual supply voltages offers freedom for placement as much as conventional ones for single supply voltage, exsting P&R tools can be used without special operation. Simulation results with MCNC circuits and adders show that our approach reduces power by 23% and 25%, respectively, showing almost the same delay with single supply voltage layout.

This paper presents an asynchronous data transfer scheme using 2-color 2-phase dual-rail encoding based on a differential operation and its circuit realization. The proposed encoding enables seamless asynchronous data transfer without inserting a spacer, because each logic value is represented by two kinds of codewords with dual-rail, called "color" data. Since the difference x-x between components of a codeword (x,x) becomes constant in every valid state, the data-arrival state can be detected by calculating the difference x-x. From the viewpoint of circuit implementation, during the state transition, since the dual-rail x and x are defined so as to transit differentially, the compatibility with a comparator using a differential amplifier becomes high, which results in reduction of the cycle time. It is evaluated using HSPICE simulation with a 0.18 µm CMOS technology that communication speed using the proposed dual-rail encoding becomes 1.4 times faster than that using conventional dual-rail encoding.

An antenna with a wide bandwidth is required for ultra-wideband (UWB) system of the future. Several types of wideband antenna that cover the whole frequency range have been proposed. Since the UWB system would cover from 3.1 to 10.6 GHz, it is necessary to suppress the interference from other systems using some of this frequency band. This paper presents two types of novel planar monopole antenna: one consists of two connected rectangular plates and another one is an orthogonal type. The return loss characteristics, radiation pattern, and current distribution of these antennas were simulated by using the FDTD method. The proposed antennas had dual frequency and broad bandwidth characteristics at both resonant frequencies. The return loss level at the eliminated frequency between the resonant frequencies was almost 0 dB. The radiation patterns for the whole frequency range were almost omni-directional in the horizontal plane. The current distributions at each frequency were similar to that of a planar rectangular monopole. The radiation patterns thus were omni-directional in the horizontal plane at each resonant frequency. Therefore, the results showed that wide bandwidth characteristics could be achieved with such antennas.

This investigation proposes a novel dual-mode patch bandpass filter (BPF) that uses defect ground structure (DGS) to suppress spurious response. The proposed dual-mode patch BPF has exhibits a wide stopband characteristic owing to that uses the bandgap resonant characteristic of DGS in the harmonic frequency of the dual-mode patch BPF. The novel proposed filter demonstrates the frequency characteristics with center frequency f0 = 2.2 GHz, 3-dB bandwidth (FBW) of 8% and wider stopband from 2.6 to 6 GHz at the level of -35 dB. The experimental and simulated results agree.

This paper describes the design of a programmable QAM transceiver for VDSL applications. A 12-b DAC with 64-dB spurious-free dynamic range (SFDR) at 75-MS/s and an 11-b ADC with 72.3-dB SFDR at 70-MS/s are integrated in this complete physical layer IC. A digital IIR notch filter is included in order to not interrupt existing amateur radio bands. The proposed dual loop AGC adjusts the gain of a variable gain amplifier (VGA) to obtain maximum SNR while avoiding saturation. Using several low power techniques, the total power consumption is reduced to 300-mW at 1.8-V core and 3.3-V I/O supplies. The transceiver is fabricated in a 0.18-µm CMOS process and the chip size is 5-mm 5-mm. This VDSL transceiver supports 13-Mbps data rate over a 9000-ft channel with a BER < 10-7.