In this paper, we propose a method to solve the distributed optimal power flow problem and discuss the associated implementation. We have combined this method with a projected Jacobi (PJ) method and a modified parallel block scaled gradient (MPBSG) method possessing decomposition effects. With the decomposition, our method can be parallel processed and is computationally efficient. We have tested our method for distributed OPF problems on numerous power systems. As seen from the simulation results, our method achieved a dramatic speed-up ratio compared with the commercial IMSL subroutines.

To clarify the correspondence between Shielding Effectiveness (SE) of shielding materials and their physical property, we propose an equivalent circuit for a shielding effectiveness test apparatus using a dual TEM cell, and show its validity. By considering the structure of dual TEM cell that consists of a pair of cells coupled via an aperture in their common wall, we defined the capacitance C and mutual inductance M, that respectively express the electric coupling and magnetic coupling between two center conductors. By the measurement of unloaded S-parameter, we determined the values of C and M for a dual TEM cell in hand. Next, the shielding material was approximated by the apparent sheet resistivity Rs, and was used in the equivalent circuit of loaded aperture. As a result, the coupling level calculated from the equivalent circuit agreed well with the measured data in frequencies below 300 MHz.

A design of a linearly-polarized non-resonant waveguide broad-wall transverse slot linear array with suppressed grating lobes is presented. Each unit element in the array consists of a transverse slot, an inductive post and a parasitic dipole-pair at a height of half of the free space wavelength. It is designed as an isolated unit without considering mutual coupling by using the Method of Moments (MoM) for radiation suppression in grating beam direction and reflection cancellation at the input. The elements thus designed are used in a travelling wave array environment. It is predicted that the reflection is less than -20 dB at 11.95 GHz while the grating lobes are suppressed by more than 15 dB. The design and the characteristics of the array are confirmed by measurements.

This paper proposes flat and hierarchical approaches for generating a minimum-width transistor placement of CMOS cells in presence of non-dual P and N type transistors. Our approaches are the first exact method which can be applied to CMOS cells with any types of structure. Non-dual CMOS cells occupy a major part of an industrial standard-cell library. To generate the exact minimum-width transistor placement of non-dual CMOS cells, we formulate the transistor placement problem into Boolean Satisfiability (SAT) problem considering the P and N type transistors individually. Using the proposed method, the transistor placement problem of any types of CMOS cells can be solved exactly. In addition, the experimental results show that our flat approach generates smaller width placement for 29 out of 103 dual cells than that of the conventional method. Our hierarchical approach reduces the runtimes drastically. Although this approach has possibility to generate wider placements than that of the flat approach, the experimental results show that the width of only 3 out of 147 cells solved by our hierarchical approach are larger than that of the flat approach.

NAT-PT and DSTM are becoming more widespread as de-facto standards for IPv6 dominant network deployment. But few researchers have empirically evaluated their performance aspects. In this paper, we compared the performance of NAT-PT and DSTM with IPv4-only and IPv6-only networks on user applications using metrics such as throughput, CPU utilization, round-trip time, and connect/request/response transaction rate.

A new dual-slope ramp (DSR) reset waveform is proposed to improve the dark room contrast ratio in AC-PDPs. The proposed reset waveform has two different voltage slopes during a ramp-up period. The first voltage slope lower than the conventional ramp voltage slope plays a role in producing the priming particles under the low background luminance, which is considered to be a kind of pre-reset discharge. On the other hand, the second voltage slope higher than the conventional ramp voltage slope produces a stable reset discharge due to the presence of the priming particles, but gives rise to a slight increase in the background luminance. Thus, a bias voltage is also applied during a part of the second voltage-slope period to adjust the background luminance and address discharge characteristics. As a result, the proposed dual-slope reset waveform can lower the background luminance without causing the discharge instability, thereby improving the high dark room contrast ratio of an AC-PDP without reducing the address voltage margin.

By inserting a slot and metallic strips at the widened stub in a single layer and fed by coplanar waveguide (CPW) transmission line, novel dual-band and broadband operations are presented. The proposed antennas are designed to have dual-band operation suitable for applications in DCS (1720-1880 MHz), PCS (1850-1990 MHz), IMT-2000 (1920-2170 MHz), and IEEE 802.11 WLAN standards in the 2.4 GHz (2400-2484 MHz) and 5.2 GHz (5150-5350 MHz) bands. The dual-band antennas are simple in design, and the two operating modes of the proposed antennas are associated with perimeter of slots and loading metallic strips, in which the lower operating band can be controlled by varying the perimeters of the outer square slot and the higher band depend on the inner slot of the widened stub. The experimental results of the proposed antennas show the impedance bandwidths of the two operating bands, determined from 10-dB return loss, larger than 61% and 27% of the center frequencies, respectively.

Normal and dual bases are two popular representation bases for elements in GF(2m). In general, each distinct representation basis has its associated different hardware architecture. In this paper, we will present a unified systolic array multiplication architecture for both normal and dual bases, such a unified multiplication architecture is termed a Hankel multiplier. The Hankel multiplier has lower space complexity while compared with other existing normal basis multipliers and dual basis multipliers.

A novel microstrip dual-mode bandpass filter with ultra-broad stopband is proposed using the aperture-backed stepped-impedance ring resonator (SIRR). This SIRR consists of low-impedance strips in the four bended corners and high-impedance strips in the four straight sides. With the cross-shaped aperture placed on the ground underneath the SIRR, the upper stopband is significantly broadened. In particular, the 2nd resonant frequency of this proposed SIRR is confirmed to exceed the four times of its 1st counterpart. The dual-mode filter with the passband of 7.5% at 1.59 GHz is then designed and implemented, demonstrating the measured stopband of 1.70-5.80 GHz and size reduction of 56.0%.

This investigation proposed a novel dual-mode circular patch bandpass filter (BPF) with enhanced stopband performance. The novelty of the proposed structure is to use a pair of square etched areas acting as a perturbation element on the circular patch resonator such that two split modes are coupled and the filter structure can be reduced. The coupling coefficients of two split modes are obtained. To improve the stopband performance, a pairs of H-shaped defected ground structure (DGS) cells are used below the input/output port to suppress the spurious response of the proposed BPF. The equivalent circuit of the DGS cell is discussed and the relations between bandstop characteristic and the suitable DGS dimensions are also investigated. The proposed BPF is demonstrated with a central frequency fo = 2.2 GHz, a 3-dB fractional bandwidth of 8% and a wider stopband of -35 dB from 2.5 to 6 GHz. Measured results of experimental filter have good agreement with the theoretical simulated results.

A 2.4/5.2 GHz CMOS dual band driver stages with integrated 5.2 GHz power amplifier is presented in this work. For more accurate simulation of high power CMOS amplifier, a re-optimized macro NMOS model is used, whose nonlinear model accuracy is enhanced and its validity is proved by comparing load pull simulation with measurement. In order to achieve band selection, it has switched matching circuits at the first stage and SPDT path switch following them. At 2.4 GHz and 5.2 GHz bands, the achieved values of Psat of the switched amplifier are 9.7 dBm and 19.5 dBm, respectively. The achieved PAE is 15.3% at 5.2 GHz.

A fully integrated clock and data recovery circuit with the proposed gated frequency detector (GFD) is presented. It has been realized in a standard 0.25-µm CMOS technology. The proposed voltage-controlled oscillator (VCO) can achieve wide operation range and reasonable conversion gain by employing the analog/digital dual loop architecture. The characteristics of small VCO gain can help to reduce loop bandwidth without enlarge the capacitors and relax the constraint on choosing the loop parameter to reduce the size of the on-chip capacitor. The proposed GFD will make the frequency lock time fixed and can avoid the harmonic locking problem in digital domain for wide data rate operations. All measured BERs are less than 10-12 with the data rate from 1.7 Gbps to 3.125 Gbps.

Trellis diagrams of lattices and the Viterbi algorithm can be used for decoding. It has been known that the numbers of states and labels at every level of any finite trellis diagrams of a lattice L and its dual L* under the same coordinate system are the same. In the paper, we present concrete expressions of the numbers of distinct paths in the trellis diagrams of L and L* under the same coordinate system, which are more concrete than Theorem 2 of [1]. We also give a relation between the numbers of edges in the trellis diagrams of L and L*. Furthermore, we provide the upper bounds on the state numbers of a trellis diagram of the lattice L1L2 by the state numbers of trellis diagrams of lattices L1 and L2.

It is well known that the trellises of lattices can be employed to decode efficiently. It was proved in [1] and [2] that if a lattice L has a finite trellis under the coordinate system , then there must exist a basis (b1,b2,,bn) of L such that Wi=span() for 1in. In this letter, we prove this important result in a completely different method, and give an efficient method to compute all bases of this type.

This paper describes a 3.5 V operation InGaP HBT MMIC power amplifier module for use in GSM/EDGE dual-mode, 900/1800/1900 MHz triple band handset applications. Conventional GSM amplifiers have a high linear gain of 40 dB or more to realize efficiency operation in large gain compression state exceeding at least 5 dB. On the other hand, an EDGE amplifier needs a linear operation to prevent signal distortion. This means that a high linear gain amplifier cannot be applied to the EDGE amplifier, because the high gain leads to the high noise power in the receive band (Rx-noise). In order to solve this problem, we have changed the linear gain of the amplifier between GSM and EDGE mode. In EDGE mode, the stage number of the amplifier changes from three to two. To reduce a high gain, the first stage transistors in the amplifier is bypassed through the diode switches. This newly proposed bypass circuit enables a high gain in GSM mode and a low gain in EDGE, thus allowing the amplifier to operate with high efficiency in both modes while satisfying the Rx-noise specification. In conclusion, with diode switches and a band select switch built on the MMIC, the module delivers a Pout of 35.5 dBm and a PAE of about 50% for GSM900, a 33.4 dBm Pout and a 45% PAE for GSM1800/1900. While satisfying an error vector magnitude (EVM) of less than 4% and a receive-band noise power of less than -85 dBm/100 kHz, the module also delivers a 29.5 dBm Pout and a PAE of over 25% for EDGE900, a 28.5 dBm Pout and a PAE of over 25% for EDGE1800/1900.

This paper presents a dual-band mixer equipped with a dual-band load using current combine technique to minimize chip area by sharing inductors for each frequency band. A systematic design methodology for the current combine load based on parasitic effect considerations is also developed. By following the proposed design procedure, the load inductance and combine capacitance for the dual-band mixer can be easily determined. A 2.4/5.2-GHz CMOS mixer design has been implemented to demonstrate the feasibility of the design technique.

A dual-mode, triple-band RF front-end receiver for GSM900, DCS1800 and WCDMA is presented in this paper. This chip uses low-IF and zero-IF receiver architectures for GSM and WCDMA respectively to fulfill the entirely different system requirements of the two standards. It consists of three parallel LNAs and down-conversion mixers with on-chip LO I/Q generations. The receiver front-end is implemented in a standard 0.25 µm CMOS process and consumes about 30-mA from a 2.7-V power supply for all modes. The measured double-side band noise figure and voltage gain are 3 dB, 36 dB for the GSM900, 5.9 dB, 31 dB for the DCS1800, and 4.3 dB, 29.6 dB for the WCDMA, respectively.

A RF front-end chip for a dual-band Global Positioning System (GPS) receiver for L1 and L2 bands is designed using 0.25 µm CMOS technology. All function blocks of the GPS front-end are integrated onto one chip. The low noise amplifier has input matching over a wide frequency range to handle the L1 and L2 bands. This receiver uses a dual-band image-reject mixer with the quadrature mixer sharing a transconductor stage. This configuration enables the RF blocks to be shared with the L1 and L2 bands. The receiver has a chip area of 3.16 mm3.16 mm, and consumes 35 mA at 2.5 V.

A new technique called the Dual Parasitic Beam (DPB) technique is proposed to suppress grating lobes in a rectangular waveguide broad wall transverse slot array. This technique involves an extra layer of parasitic strip dipoles that generate the DPB to suppress the grating lobes without opposing the main beam of the original slot linear array. A full wave EM analysis in Method of Moments (MoM) is conducted to compute the coupling excitation coefficients as well as the far field patterns of the slot and dipole currents. Analysis shows that a suitable dimension and arrangement of dipoles are needed to get a desired level of dipole excitations to meet the grating suppression condition. It is found that the grating lobes can be suppressed as much as 15 dB in the presence of the parasitic dipoles. Experiments are conducted to confirm the computed results.

The goal of gaze detection is to locate the position (on a monitor) where a user is looking. Previous researches use one wide view camera, which can capture the user's entire face. However, the image resolution is too low with such a camera and the fine movements of user's eye cannot be exactly detected. So, we propose the new gaze detection system with dual cameras (a wide and a narrow view camera). In order to locate the user's eye position accurately, the narrow-view camera has the functionalities of auto focusing/panning/tilting based on the detected 3D eye positions from the wide view camera. In addition, we use the IR-LED illuminators for wide and narrow view camera, which can ease the detecting of facial features, pupil and iris position. To overcome the problem of specular reflection on glasses by illuminator, we use dual IR-LED illuminators for wide and narrow view camera and detect the accurate eye position, which is not hidden by the specular reflection. Experimental results show that the gaze detection error between the computed positions and the real ones is about 2.89 cm of RMS error.