We detail a self synchronous field programmable gate array (SSFPGA) with dual-pipeline (DP) architecture to conceal pre-charge time for dynamic logic, and its throughput optimization by using pipeline alignment implemented on benchmark circuits. A self synchronous LUT (SSLUT) consists of a three input tree-type structure with 8 bits of SRAM for programming. A self synchronous switch box (SSSB) consists of both pass transistors and buffers to route signals, with 12 bits of SRAM. One common block with one SSLUT and one SSSB occupies 2.2 Mλ2 area with 35 bits of SRAM, and the prototype SSFPGA with 3430 (1020) blocks is designed and fabricated using 65 nm CMOS. Measured results show at 1.2 V 430 MHz and 647 MHz operation for a 3 bit ripple carry adder, without and with throughput optimization, respectively. We find that using the proposed pipeline alignment techniques we can perform at maximum throughput of 647 MHz in various benchmarks on the SSFPGA. We demonstrate up to 56.1 times throughput improvement with our pipeline alignment techniques. The pipeline alignment is carried out within the number of logic elements in the array and pipeline buffers in the switching matrix.

This paper treats a band-broadening design technique of a dual-band branch-line coupler with matching networks composed of an impedance step and a short-circuited stub based on the equivalent admittance approach. By replacing each right-handed transmission line (RH-TL) with a composite right/left-handed transmission line (CRLH-TL), very flat couplings over a relative bandwidth of about 10% can be obtained at two arbitrary operating frequencies in comparison with previous CRLH-TLs branch-line couplers. Furthermore, by adding periodical open-circuited stubs into RH-TLs of the designed CRLH-TLs branch-line coupler with matching networks, the entire size of the coupler can be reduced to about 50%. Verification of these band-broadening and size-reduction design techniques can be also shown by an electromagnetic simulation and experiment.

Since the length of wires between different layers, even between the top and bottom layers, is acceptably small in 3D mesh-based NoC (three-Dimensional mesh-based Network on Chip), a structure in which an IP (Intelligence Property) core in a certain layer directly connected to a proper router in another layer may efficiently decrease the average latency of messages and increase the maximum throughput. With this idea, in the paper, we introduce a dual-port access structure, in which each IP core except that in the bottom layer is connected to two routers in two adjacent layers, and, in particular, the IP core in the bottom layer can be directly connected to the proper router in the top layer. Furthermore, we derive the close form expression of the average number of hops of messages and also give the quantitative analysis of the performance when the dual-port access structure is used. All the analytical results reveal that the average number of hops is reduced and the system performance is improved, including a decrease of average latency and an increase of maximum throughput. Finally, the simulation results confirm our theoretical analysis and show the advantage of the proposed dual-port access structure with a relatively small increment of area overhead.

The multilevel dual-channel (MLDC) not-AND (NAND) flash memories cell structures with asymmetrically-doped channel regions between the source and the drain were proposed to enhance read and program verifying speeds. The channel structure of the MLDC flash memories consisted of two different doping channel regions. The technical computer aided design simulation results showed that the designed MLDC NAND flash cell with asymmetrically-doped channel regions provided the high-speed multilevel reading with a wider current sensing margin and the high-speed program verifying due to the sensing of the discrete current levels. The proposed unique MLDC NAND flash memory device can be used to increase read and program verifying speed.

In this letter, a novel technique for fast block matching using a new matching criterion is proposed. The matching speed and image quality are controlled by the one control parameter called matching region ratio. An efficient matching scheme with a gradual voting strategy is also proposed. This scheme can greatly boost the matching speed. The proposed technique is fast and applicable even in the presence of speckle noise or partial occlusion.

In this Letter, a residual acoustic echo suppression method is proposed to enhance the speech quality of hands-free communication in an automobile environment. The echo signal is normally a human voice with harmonic characteristics in a hands-free communication environment. The proposed algorithm estimates the residual echo signal by emphasizing its harmonic components. The estimated residual echo is used to obtain the signal-to-interference ratio (SIR) information at the acoustic echo canceller output. Then, the SIR based Wiener post-filter is constructed to reduce both the residual echo and noise. The experimental results confirm that the proposed algorithm is superior to the conventional residual echo suppression algorithm in terms of the echo return loss enhancement (ERLE) and the segmental signal-to-noise ratio (SEGSNR).

In this paper, we study the performance of dual hop relaying in which the best relay selected by partial relay selection will help the source-destination link to overcome the channel impairment. Specifically, closed-form expressions for outage probability, symbol error probability and achievable diversity gain are derived using the statistical characteristic of the signal-to-noise ratio. Numerical investigation shows that the system achieves diversity of two regardless of relay number and also confirms the correctness of the analytical results. Furthermore, the performance loss due to partial relay selection is investigated.

A neutralization line is internally added to a 770 MHz LTE-band miniature dual-antenna system to improve its antenna efficiency. The odd-mode antenna impedance simulations indicate that the position of the neutralization line along the radiating structure determines the operation frequency. Measurement results show that the line reduces the antenna coupling loss from -6 to -17 dB while improving the individual antenna efficiency from 42 to 65 percent at 770 MHz.

A novel 300 MHz embedded flash memory for dual-core microcontrollers with a shared ROM architecture is proposed. One of its features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduces performance penalty due to conflict of shared ROM accesses. Another feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch as a result of a shortened sense time of 0.63 ns. The combination of the pipeline architecture and proposed sense amplifiers significantly reduces access-conflict penalties with shared ROM and enhances performance of 32-bit RISC dual-core microcontrollers by 30%.

This paper clarifies the adequacy of the linear channel coding approach for Slepian-Wolf coding of individual sequences. A sufficient condition for ensembles of linear codes from which a universal Slepian-Wolf code can be constructed is given. Our result reveals that an ensemble of LDPC codes gives a universal code for Slepian-Wolf coding of individual sequences.

This letter presents the construction and design equations of a lumped element Wilkinson divider with dual-band operation. This divider is constructed of series and parallel LC resonant circuits, and an isolation resistor. The element values can be uniquely determined by giving the two frequencies for operation as a Wilkinson divider and the load resistance. An 800 MHz/2 GHz dual-band Wilkinson divider is treated as a design example, and its operation is verified by simulation and experiment. The fabricated divider has compact dimensions of 3.564 mm2.

This paper presents the dual-band bandpass filters (BPFs) design composed of λ/2 and symmetrically/asymmetrically paired λ/4 stepped impedance resonators (SIRs) for the WLAN applications. The filters cover both the operating frequencies of 2.45 and 5.2 GHz. The dual-coupling mechanism is used in the filter design to provide alternative routes for signals of selected frequencies. A prototype filter is composed of λ/2 and symmetrical λ/4 SIRs. The enhanced wide-stopband filter is then developed from the filter with the symmetrical λ/4 SIRs replaced by the asymmetrical ones. The asymmetrical λ/4 SIRs have their higher resonances frequencies isolated from the adjacent I/O SIRs and extend the enhanced filter an upper stopband limit beyond ten time the fundamental frequency. Also, the filter might possess a cross-coupling structure which introduces transmission zeros by the passband edges to improve the signal selectivity. The tapped-line feed is adopted in this circuit to create additional attenuation poles for improving the stopband rejection levels. Experiments are conducted to verify the circuit performance.

In this Letter, a robust system identification method is proposed for the generalized sidelobe canceller using dual microphones. The conventional transfer-function generalized sidelobe canceller employs the non-stationarity characteristics of the speech signal to estimate the relative transfer function and thus is difficult to apply when the noise is also non-stationary. Under the assumption of W-disjoint orthogonality between the speech and the non-stationary noise, the proposed algorithm finds the speech-dominant time-frequency bins of the input signal by inspecting the system output and the inter-microphone time delay. Only these bins are used to estimate the relative transfer function, so reliable estimates can be obtained under non-stationary noise conditions. The experimental results show that the proposed algorithm significantly improves the performance of the transfer-function generalized sidelobe canceller, while only sustaining a modest estimation error in adverse non-stationary noise environments.

Modular multiplication is the most dominant arithmetic operation in elliptic curve cryptography (ECC), that is a type of public-key cryptography. Montgomery multiplier is commonly used to compute the modular multiplications and requires scalability because the bit length of operands varies depending on its security level. In addition, ECC is performed in GF(P) or GF(2n), and unified architecture for multipliers in GF(P) and GF(2n) is required. However, in previous works, changing frequency is necessary to deal with delay-time difference between GF(P) and GF(2n) multipliers because the critical path of the GF(P) multiplier is longer. This paper proposes unified dual-radix architecture for scalable Montgomery multiplications in GF(P) and GF(2n). This proposed architecture unifies four parallel radix-216 multipliers in GF(P) and a radix-264 multiplier in GF(2n) into a single unit. Applying lower radix to GF(P) multiplier shortens its critical path and makes it possible to compute the operands in the two fields using the same multiplier at the same frequency so that clock dividers to deal with the delay-time difference are not required. Moreover, parallel architecture in GF(P) reduces the clock cycles increased by dual-radix approach. Consequently, the proposed architecture achieves to compute a GF(P) 256-bit Montgomery multiplication in 0.28 µs. The implementation result shows that the area of the proposal is almost the same as that of previous works: 39 kgates.

A simple and novel residual acoustic echo cancellation method that employs binary masking is proposed to enhance the speech quality of hands-free communication in an automobile environment. In general, the W-disjoint orthogonality assumption is used for blind source separation using multi-microphones. However, in this Letter, it is utilized to mask the residual echo component in the time-frequency domain using a single microphone. The experimental results confirm the effectiveness of the proposed method in terms of the echo return loss enhancement and speech enhancement.

Dual-band chip antennas usually have a narrow bandwidth in the first resonance frequency band due to an inter-coupling capacitance. In order to analyze the effect of the inter-coupling capacitance, an equivalent circuit of an antenna with a branch radiator is considered in this paper. Based on the equivalent circuit model, it is found that the inter-coupling capacitance reduces impedance bandwidth. This paper proposes a gap feeding method to alleviate the effect of the inter-coupling capacitance and explains it using an equivalent circuit.

In this letter, we present the impact of carrier frequency offset (CFO) in dual-hop orthogonal frequency division multiplexing (OFDM) systems with a fixed relay for frequency-selective fading channels. Approximate expressions of the average signal-to-noise ratios (SNRs) for both downlink and uplink are obtained and validated by simulations. It is shown that dual-hop systems have slightly worse average SNR degradation than single-hop systems. We also show that the average SNR degradation due to the CFO varies according to the gap between average received SNRs for the first and the second hop.

This paper presents a multi functional range finder employing dual imager core on a single chip. Each imager core has functionalities of 2-D imaging and 3-D capture using the light section method with combinations of the dual imager core. The presented chip achieves, 2-D imaging mode, 3-D capture mode with the conventional light-section method, high-speed 3-D capture mode with the stereo matching mode, and 2-D and 3-D simultaneous capture mode. We demonstrate 58 fps 2-D imaging with 8 bit gray scale, and 24.8 rangemaps/s 3-D range-finder with the maximum range error of 1.619 mm and the standard deviation of 0.385 mm at 700 mm.

In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents and shorter delays than conventional CMOS gates. Compared with the conventional 65 nm CMOS gates, our proposed 65 nm gates in this paper can improve leakage currents, dynamic power consumption, and propagation delays by averages of 42.4%, 8.1%, and 13.5%, respectively. Logic synthesizers can use them to facilitate power reduction. The experimental results show that a commercial power optimization tool can further reduce the leakage current and dynamic power up to 39.85% and 18.69%, respectively, when the standard cell library used by the tool contains our proposed gates.

A dual band 0.18 µm CMOS LC-tank injection locked frequency divider (ILFD) is proposed. The ILFD circuit is realized with a cross-coupled pMOS LC-tank oscillator with an inductor switch for frequency band selection. The self-oscillating VCO is injection-locked by nth-harmonic input to obtain the division factor of n. The division ratio of 1, 2, and 3 has been found for the proposed ILFD. Measurement results show that at the supply voltage of 1.1 V, the free-running frequency is from 2.28(3.09) GHz to 2.78(3.72) GHz for the low- (high-) frequency band. The power consumption of the ILFD core is 3.7 mW (6.2 mW) at low (high) band. The total area including the output buffer and the pads is 0.8410.764 mm2.