The voltage island style has been widely accepted as an effective way to design low power high performance chips. This paper proposes an automated voltage island generation flow in standard cell based designs. Two important objectives in voltage island designs are addressed in this flow: 1) reducing power dissipation under given performance constraints; 2) reducing implementation overheads, mainly layout overheads caused by cell clustering to form islands. The first objective is handled with timing and power driven netweighting and timing analysis in voltage assignment. For the second objective, we propose layout aware voltage assignment, i.e., voltage assignment during placement. We iteratively perform the following to adjustments: adjustment on voltage assignment to facilitate voltage island generation, and adjustment on cell locations to cluster cells in voltage islands. These iterations lead to a flow featured with tightly integrated voltage assignment and cell placement. Experimental results have demonstrated the advantages of our approach.

Novel dual-band bandpass filter (BPF) with quasi-elliptic function response by using the meander coupled step-impedance resonators (SIRs) is presented. By tuning the appropriate impedance ratio (K) and physical length of SIRs, the BPF has good dual-band performance at 2.4 and 5.2 GHz with high selectivity, due to the transmission zeros appeared in two passband edges. Measured results of the proposed BPF have a good agreement with the electromagnetic (EM) simulated results.

We propose a new method of logic synthesis for dual-rail RSFQ (rapid single-flux-quantum) digital circuits. RSFQ circuit technology is one of the strongest candidates for the next generation technology of digital circuits. For representing logic functions, we use a root-shared binary decision diagram (RSBDD) which is a directed acyclic graph constructed from binary decision diagrams. In the method, first we construct an RSBDD from given logic functions, and then reduce the number of nodes in the constructed RSBDD by variable re-ordering. Finally, we synthesize a dual-rail RSFQ circuit from the reduced RSBDD. We have implemented the method and have synthesized benchmark circuits. We have synthesized dual-rail circuits that consist of about 27% fewer logic elements than those synthesized by a Transduction-based method on average.

A new 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit is realized. To overcome jitter problems caused by the phase resolution limit, the CDR has two phase generation stages: coarse generation by a phase interpolator and fine generation by a variable delay buffer. The performance of the proposed CDR was verified by behavioral and transistor-level simulations. A prototype CDR chip fabricated with 0.18 µm CMOS process shows error-free operation for 400 ppm frequency offset. The chip occupies 165255 µm2 and consumes 17.8 mW.

This paper presents the design, fabrication and characterization of a low actuation voltage capacitive shunt RF-MEMS switch for microwave and millimeter-wave applications based on a corrugated electrostatic actuated bridge suspended over a concave structure of coplanar waveguide (CPW), with sputtered nickel as the structural material for the bridge and gold for CPW line, fabricated on high-resistivity silicon (HRS) substrate using IC compatible processes for modular integration in a communication devices. The residual stress is very low because having both ends corrugated structure of the bridge in concave structure. The residual stress is calculated about 3-15 MPa in corrugated bridge and 30 MPa in flat bridge. The corrugated bridge of the concave structure requires lower actuation voltages 20-80 V than 50-100 V of the flat bridge of the planar structure in 0.3 to 1.0 µm thick Ni capacitive shunt RF-MEMS switch, in insertion loss 1.0 dB, return loss 12 dB, power loss 10 dB and isolation 28 dB from 0.5 up to 40 GHz. The residual stress of the bridge material and structure is critical to lower the actuation voltage.

A novel wideband bandpass filter with improved stopband characteristics is presented in this paper. Dual-mode square ring resonator is used in the proposed filter. New formulas based on the even- and odd-mode analysis are derived to facilitate the design of transmission zeros of the square ring resonator. A short-circuited stub and a piece of aperture-enhanced parallel-coupled lines are introduced to the input and output of the resonator to lower the passband return loss and widen the stopband of the filter significantly. The filter has a 50% fractional bandwidth, is compact in configuration, and shows remarkably improved performance compared with previously reported filters of the same kind. The measured filtering response shows a good agreement with the simulated result.

As VLSI technology advances, delay variations will become more serious. Delay-insensitive asynchronous dual-rail circuits tolerate any delay variation, but their energy consumption is more than double that of the single-rail circuits because signal transitions occur every cycle in all bits regardless of the input bit pattern. However, in functional units, a significant number of input bits may not change from the previous input in many cases. In such a situation, calculation of these bits is not required. Thus, we propose a method, called unflip-bits control, makes use of the above situation, to reduce energy consumption. We evaluate the energy consumption and performance penalty for the method using HSPICE and the verilog-XL simulator, and compare the method with the conventional dual-rail circuit and a synchronous circuit. Our evaluation results reveal that the proposed asynchronous dual-rail circuit has a 12-60% lower energy consumption compared with a conventional asynchronous dual-rail circuit.

This paper presents an asynchronous multiple-valued current-mode data-transfer controller chip based on a 1-phase dual-rail encoding technique. The proposed encoding technique enables "one-way delay" asynchronous data transfer because request and acknowledge signals can be transmitted simultaneously and valid states are detected by calculating the sum of dual-rail codewords. Since a key component, a current-to-voltage conversion circuit in a valid-state detector, is tuned so as to obtain a sufficient voltage range to improve switching speed of a comparator, signal detection can be performed quickly in spite of using 6-level signals. It is evaluated using HSPICE simulation with a 0.18-µm CMOS that the throughput of the proposed circuit based on the 1-phase dual-rail scheme attains 435 Mbps/wire which is 2.9 times faster than that of a CMOS circuit based on a conventional 4-phase dual-rail scheme. The test chip is fabricated, and the asynchronous data-transfer behavior of the proposed scheme is confirmed.

In this paper, we propose two techniques to solve the nonlinear constrained optimization problem in large scale mesh-interconnected system. The first one is a diagram-method-based decomposition technique which decomposes the large scale system into some small subsystems. The second technique is a projected-Jacobi-based parallel dual-type method which can solve the optimization problems in the decomposed subsystems efficiently. We have used the proposed algorithm to solve numerous examples of large scale constrained optimization problems in power system. The test results show that the proposed algorithm has computational efficiency with respect to the conventional approach of the centralized Newton method and the state-of-the-art Block-Parallel Newton method.

A systematic approach to the analysis and design of a bi-directional Cuk converter for the cell voltage balancing control of a series-connected lithium-ion battery string is presented in this paper. The proposed individual cell equalizers (ICE) are designed to operate at discontinuous-capacitor-voltage mode (DCVM) to achieve the zero-voltage switching (ZVS) for reducing the switching loss of the bi-directional DC/DC converters. Simulation and experimental results show that the proposed battery equalization scheme can not only enhance the bi-directional battery equalization performance, but also can reduce the switching loss during the equalization period. Two designed examples are demonstrated, the switch power losses are significantly reduced by 52.8% from the MOSFETs and the equalization efficiency can be improved by 68-86.9% using the proposed DCVM ZVS battery equalizer under the specified cell equalization process. The charged/discharged capacity of the lithium-ion battery string is increased by using the proposed ICEs equipped in the battery string.

This investigation proposes a modified equivalent circuit of single complementary split-ring resonator (CSRR) in planar transmission media and a dual-mode ring bandpass filter (BPF) that uses periodic CSRRs to suppress the spurious response. The proposed modified equivalent circuit consists of lumped elements that can be easily extracted from the measured S parameters. The proposed dual-mode ring BPF has exhibits a wide stopband characteristic owing to the bandgap resonant characteristic of CSRRs in the harmonic frequency of the dual-mode ring BPF. Good agreement with EM simulation and measurement is demonstrated.

This paper investigates some relations among four complexities of sequence over countably infinite alphabet, and shows that two kinds of empirical entropies and the self-entropy rate regarding a Markov source are asymptotically equal and lower bounded by the maximum number of phrases in distinct parsing of the sequence. Some connections with source coding theorems are also investigated.

In orthogonal frequency-division multiplexing (OFDM)-based wireless local area networks (WLANs), phase noise (PHN) and residual frequency offset (RFO) can cause the common phase error (CPE) and the inter-carrier interferences (ICI), which seriously degrade the performance of systems. In this letter, we propose a combined pilot symbol assisted and decision-directed channel estimation scheme based on the least-squares (LS) and the maximum-likelihood (ML) algorithms. Simulation results present that the proposed scheme significantly improves the performance of OFDM-based WLANs.

This paper presents a design procedure of multilayer single-input/single-output dual-band filters of small size fabricated in high-permittivity LTCC (Low Temperature Co-fired Ceramic) substrates. The present dual-band filter, with pass bands of 950 MHz and 1.9 GHz, consists of two single-band filters each one of which has a matching circuit for controlling the input impedance in the pass band of the counterpart. Discussed first in this paper is a dual-band filter that has the matching circuit connected to the single-band filters externally. Then, a dual-band filter with the matching circuit embedded in its body is investigated together with metallization patterns of the matching elements. Presented finally is a very small single-input/single-output dual-band filter suitable for dual-band wireless communication systems.

This letter evaluates the performance of an uplink multicarrier-code division multiple access (MC-CDMA) system when the frequency offsets of all users are random variables and the frequency offset for the desired user is compensated. The analysis confirms that performance degradation due to frequency offset is negligible if the estimation error of normalized frequency offset for the desired user is less than 10-1.

Two compact and low loss dual-mode filters are proposed by using degenerate modes of slotted triangular microstrip patch resonators. The geometrical size and radiation loss of the triangular patch are reduced simultaneously by loading both horizontal and vertical slots. The resonant frequencies of two degenerate modes can be easily controlled by varying the dimensions and positions of the slots. A two-pole dual-mode filter operating at 3.94 GHz with a fractional bandwidth of 4.3% is designed, fabricated, and measured. The measured results verify well the theoretical predictions.

A novel method is proposed to synthesize dual-band bandpass filters (BPFs) from a prototype lowpass filter. By implementing successive frequency transformations and circuit conversions, a new filter topology is obtained which consists of only admittance inverters and series or shunt resonators, and is thereby easy to be realized by using conventional distributed elements. A microstrip dual-band BPF with central frequencies of 1.8 GHz and 2.4 GHz is designed and fabricated using microstrip lines and stubs. The simulated and measured results show a good agreement and validate thereby the proposed theory.

A comparison of performances is made of three text-independent speaker identification methods based on dual Penalized Logistic Regression Machine (dPLRM), Support Vector Machine (SVM) and Gaussian Mixture Model (GMM) with experiments by 10 male speakers. The methods are compared for the speech data which were collected over the period of 13 months in 6 utterance-sessions of which the earlier 3 sessions were for obtaining training data of 12 seconds' utterances. Comparisons are made with the Mel-frequency cepstrum (MFC) data versus the log-power spectrum data and also with training data in a single session versus in plural ones. It is shown that dPLRM with the log-power spectrum data is competitive with SVM and GMM methods with MFC data, when trained for the combined data collected in the earlier three sessions. dPLRM outperforms GMM method especially as the amount of training data becomes smaller. Some of these findings have been already reported in [1]-[3].

Novel microstrip dual-band bandpass filters with controllable fractional bandwidths and good in-between isolation are presented and implemented. A half-wavelength stepped-impedance resonator is firstly characterized, aiming at producing the two resonant frequencies at 2.4 and 5.2 GHz. Two types of coupled microstrip lines in the parallel and anti-parallel formats are then investigated in terms of unified equivalent J-inverter network. Extensive results are derived to quantitatively show their distinctive frequency-distributed coupling performances under different coupling lengths. The coupling degrees of these two coupled lines at the two resonances are properly adjusted to achieve the dual-passband response with varied or tunable bandwidths. In addition, the parallel coupled line is modeled to bring out a transmission zero between the two resonances so as to achieve the good in-between isolation. The three two-stage bandpass filters are initially designed to exhibit their dual-band response with changeable dual-band bandwidths. A three-stage dual-band filter is in final optimally designed and its predicted performance is confirmed in experiment.

In everyday life, a situation often occurs wherein two or more persons with different personal schedules must determine a single job schedule. The authors focus on the practical concept of rent and loan and propose a scheduling system. This system generates a schedule that automatically coordinates with a state involving minimum rent and loan. They also propose a method that employs the analytic network process (ANP) for setting individual priorities based on the rent and loan information. Furthermore, the authors implement the proposed system as a simulation system and verify whether it generates a fair schedule by computing the sum of the rent and loan of different individuals. The result shows that in comparison with human scheduling, the proposed method generates a fairer schedule by computing the rent and loan of each individual.