Let Fq be a finite field of cardinality q, R=Fq[u]/=Fq+uFq+u2Fq+u3Fq (u4=0) which is a finite chain ring, and n be a positive integer satisfying gcd(q,n)=1. For any $delta,alphain mathbb{F}_{q}^{ imes}$, an explicit representation for all distinct (δ+αu2)-constacyclic codes over R of length n is given, and the dual code for each of these codes is determined. For the case of q=2m and δ=1, all self-dual (1+αu2)-constacyclic codes over R of odd length n are provided.

A frequency-reconfigurable dipole antenna, whose dual resonant frequencies are independently controlled, is introduced. The antenna's conductor consists of radiating conductors, lumped and distributed elements, and varactors. To design the antenna, current distribution, input impedance, and radiation power including higher-order modes, are analyzed for a narrow-angle sectorial antenna embedded with passive elements. To derive the formulae used, radiation power is analyzed in two ways: using Chu's equivalent circuit and the multipole expansion method. Numerical estimations of electrically small antennas show that dual-band antennas are feasible. The dual resonant frequencies are controlled with the embedded series and shunt inductors. A dual-band antenna is fabricated, and measured input impedances agree well with the calculated data. With the configuration, an electrically small 2.5-/5-GHz dual-band reconfig-urable antenna is designed and fabricated, where the reactance values for the series and shunt inductors are controlled with varactors, each connected in series to the inductors. Varying the voltages applied to the varactors varies the measured upper and lower resonant frequencies between 2.6 and 2.9GHz and between 5.1 and 5.3GHz, where the other resonant frequency is kept almost identical. Measured radiation patterns on the H-plane are almost omni-directional for both bands.

A compact millimeter-wave three-pole dual-band bandpass filter (BPF) by using substrate-integrated waveguide (SIW) dual-mode cavities is developed in this paper. The proposed filter consists of three SIW dual-mode cavities, in which the TE201 and TE102 modes are used to form two passbands. The center frequencies of the two passbands can be readily changed by varying the lengths and/or widths of the SIW cavities. Meanwhile three transmission zeros are produced with appropriate design of the input and output of the SIW cavities, which increase significantly the isolation between the two passbands and their roll-off rate of attenuations. The dual-band BPF filter is designed, fabricated and measured. The measured center frequencies of the two passbands are 26.75GHz and 31.55GHz, respectively. The 3dB-passbands are 26.35-27.15GHz (3%) and 31.29-31.81GHz (1.6%), respectively, with maximum insertion loss of 2.64dB and 4.2dB, respectively, and return loss larger than 12dB in both passbands. A good agreement between the simulated and measured filter characteristics is obtained.

The high-availability seamless redundancy (HSR) protocol is a representative protocol that fulfills the reliability requirements of the IEC61850-based substation automation system (SAS). However, it has the drawback of creating unnecessary traffic in a network. To solve this problem, a dual virtual path (DVP) algorithm based on HSR was recently presented. Although this algorithm dramatically reduces network traffic, it does not consider the substation timing requirements of messages in an SAS. To reduce unnecessary network traffic in an HSR ring network, we introduced a novel packet transmission (NPT) algorithm in a previous work that considers IEC61850 message types. To further reduce unnecessary network traffic, we propose an extended dual virtual paths (EDVP) algorithm in this paper that considers the timing requirements of IEC61850 message types. We also include sending delay (SD), delay queue (DQ), and traffic flow latency (TFL) features in our proposal. The source node sends data frames without SDs on the primary paths, and it transmits the duplicate data frames with SDs on the secondary paths. Since the EDVP algorithm discards all of the delayed data frames in DQs when there is no link or node failure, unnecessary network traffic can be reduced. We demonstrate the principle of the EDVP algorithm and its performance in terms of network traffic compared to the standard HSR, NPT, and DVP algorithm using the OPNET network simulator. Throughout the simulation results, the EDVP algorithm shows better traffic performance than the other algorithms, while guaranteeing the timing requirements of IEC61850 message types. Most importantly, when the source node transmits heavy data traffic, the EDVP algorithm shows greater than 80% and 40% network traffic reduction compared to the HSR and DVP approaches, respectively.

As dual-polarized multiple-input multiple-output (MIMO) technique has little inter-antenna interference, it provides high data rate and reliability to a user equipment (UE) with the low system complexity. In the joint transmission (JT) technique of the coordinated multi-point (CoMP) transmission system, multiple transmission points (TPs) transmit the same data to the UE so that the UE can get the diversity gain and the high reliability, especially at the cell-edge. However, the system performance of the dual-polarized MIMO in the JT technique of CoMP system is very sensitive on the dual-polarized channel state when the channel is asymmetric. In this letter, an improved dual-polarized MIMO scheme for JT of the downlink CoMP transmission system is proposed. This scheme adaptively applies the transmission power to each dual-polarized MIMO antenna and the modulation order of the transmission data according to the channel state information (CSI). System-level simulation results show that the proposed scheme provides better bit-error-rate (BER) performance in the asymmetric dual-polarized channel state than the conventional scheme.

In this letter, a novel perceptually motivated single channel speech enhancement approach based on Deep Neural Network (DNN) is presented. Taking into account the good masking properties of the human auditory system, a new DNN architecture is proposed to reduce the perceptual effect of the residual noise. This new DNN architecture is directly trained to learn a gain function which is used to estimate the power spectrum of clean speech and shape the spectrum of the residual noise at the same time. Experimental results demonstrate that the proposed perceptually motivated speech enhancement approach could achieve better objective speech quality when tested with TIMIT sentences corrupted by various types of noise, no matter whether the noise conditions are included in the training set or not.

Cache memories are the major application of high-speed SRAMs, and they are frequently installed in high performance logic VLSIs including microprocessors. This paper presents a 4-way set-associative, SOI cache-tag memory. To obtain higher operating speed with less power dissipation, we devised an I/O-separated memory cell with a dual-rail wordline, which is used to transmit complementary selection signals. The address decoding delay was shortened using CMOS dual-rail logic. To enhance the maximum operating frequency, bitline's recovery operations after writing data were eliminated using a memory array configuration without half-selected cells. Moreover, conventional, sensitive but slow differential amplifiers were successfully removed from the data I/O circuitry with a hierarchical bitline scheme. As regards the stored data management, we devised a new hardware-oriented LRU-data replacement algorithm on the basis of 6-bit directed graph. With the experimental results obtained with a test chip fabricated with a 0.25-µm CMOS/SIMOX process, the core of the cache-tag memory with a 1024-set configuration can achieve a 1.5-ns address access time under typical conditions of a 2-V power supply and 25°C. The power dissipation during standby was less than 14 µW, and that at the 500-MHz operation was 13-83 mW, depending on the bit-stream data pattern.

This paper proposes an application of splitting source-node power for a two-phase cooperative relaying system where the transmit powers of the source and the relay node are individually constrained. In the proposed usage, the limited source power is divided into two parts that are used in the first and the second phase. Unlike conventional relaying methods, in the second phase the source retransmits its signal with the split power and, at the same time, the relay forwards the signal received at the first phase, which causes interference between the signals. In order to avoid the intervention, so-called a co-phasing weight for aligning the phases of the two signals is used at at the source before the second transmission. The forwarding operation at the relay however is exactly the same as the conventional techniques. Optimal power-splitting as well as the co-phasing weight is provided in this paper. With numerical investigation, the proposed power-splitting is shown to significantly improve the achievable throughput as well as reduce the outage probability compared with the conventional individual power allocation.

A novel high common-mode (CM) suppression wideband balanced passband filter (BPF) is proposed using the stub centrally loaded slotline resonators (SCLSR) which have two resonant frequencies (odd- and even-modes) in the desired passband. The odd-mode resonant frequency of the slotline SCLSR can be flexibly controlled by the stub, whereas the even-mode one is fixed. Meanwhile, a transmission zero near the odd-mode resonant frequency can be generated due to the main path signal counteraction. First, the wideband single-ended BPF and corresponding balanced BPF are designed based on the slotline SCLSR with the parallel coupled microstrip line input/output (I/O). Ultra wideband high CM suppression that can be achieved for the slotline resonator structure has no resonant mode under CM excitation. Furthermore, by folding the parallel coupled microstrip line I/O, the source-load coupling is effectively decoupled to improve the CM suppression within the passband. The high suppression wideband balanced BPF is fabricated and measured, respectively. Good agreement between simulation and measurement results is obtained.

In indoor localization using sensor networks, performance improvements are required for non-line-of-sight (NLOS) environments in which the estimation error is high. NLOS mitigation schemes involve the detection and elimination of the NLOS measurements. The iterative minimum residual (IMR) scheme, which is often applied to the localization scheme using the time of arrival (TOA), is commonly employed for this purpose. The IMR scheme is a low-complexity scheme and its NLOS detection performance is relatively high. However, when there are many NLOS nodes in a sensor field, the NLOS detection error of the IMR scheme increases and the estimation accuracy deteriorates. Therefore, we propose a new scheme that exploits coarse NLOS detection based on stochastic characteristics prior to the application of the IMR scheme to improve the localization accuracy. Improved performances were confirmed in two NLOS channel models by performing numerical simulations.

In this article, we study skew cyclic codes over $R=mathbb{F}_{q}+vmathbb{F}_{q}+v^{2}mathbb{F}_{q}$, where $q=p^{m}$, $p$ is an odd prime and v3=v. We describe the generator polynomials of skew cyclic codes over this ring and investigate the structural properties of skew cyclic codes over R by a decomposition theorem. We also describe the generator polynomial of the dual of a skew cyclic code over R. Moreover, the idempotent generators of skew cyclic codes over $mathbb{F}_{q}$ and R are considered.

RXv2 is the new generation of Renesas's processor architecture for microcontrollers with high-capacity flash memory. An enhanced instruction set and pipeline structure with an advanced fetch unit (AFU) provide an effective balance between power consumption performance and high processing performance. Enhanced instructions such as DSP function and floating point operation and a five-stage dual-issue pipeline synergistically boost the performance of digital signal applications. The RXv2 processor delivers 1.9 - 3.7 the cycle performance of the RXv1 in these applications. The decrease of the number of Flash memory accesses by AFU is a dominant determiner of reducing power consumption. AFU of RXv2 benefits from adopting branch target cache, which has a comparatively smaller area than that of typical cache systems. High code density delivers low power consumption by reducing instruction memory bandwidth. The implementation of RXv2 delivers up to 46% reduction in static code size, up to 30% reduction in dynamic code size relative to RISC architectures. RXv2 reaches 4.0 Coremark per MHz and operates up to 240MHz. The RXv2 processor delivers approximately more than 2.2 - 5.7x the power efficiency of the RXv1. The RXv2 microprocessor achieves the best possible computing performance in various applications such as building automation, medical, motor control, e-metering, and home appliances which lead to the higher memory capacity, frequency and processing performance.

Novel multi-band mixers that can receive multiple band signals concurrently are proposed and evaluated. The mixers achieve independent gain control through novel relative power control method of the multiple local oscillator (LO) signals. Linear control is also achieved through multiple LO signal input with total LO power control. Theoretical analysis shows that odd-order nonlinearity components of the multiple LO signals support linear conversion gain control. Dual- and triple-band tests are conducted using typical three MOSFET mixers fabricated by a 0.25 µm SiGe BiCMOS process. Measurements confirm over 40 dB independent control of conversion gain, linear control achieved through LO input power control. The proposed mixers have high input linearity with a 5 dBm output third intercept point. A method is also proposed to reduce interference caused by mixing between multiple LO signals.

This paper considers a method for constructing good high-rate punctured convolutional codes through dual codes. A low-rate R=1/n convolutional code has a dual code identical to a punctured convolutional code with rate R=(n-1)/n. This implies that a low-rate R=1/n convolutional code encoder can help the search of punctured convolutional code encoders. This paper provides the procedures that obtain all the useful dual code encoders to a given CC with rate R=1/n easily, and the best PCC encoder with rate R=(n-1)/n among the encoders we derive from all the obtained dual code encoders. This paper also shows an example of the PCC the procedures obtain from some CC.

Dense millimeter-wave networks are a promising candidate for next-generation cellular systems enabling multiple gigabit-per-second data rates. A major disadvantage of millimeter-wave systems is signal disruption by rain, and here we propose a novel method for rain sensing using dual-frequency measurements at 25 and 38GHz from a small-scale Tokyo Institute of Technology (Tokyo Tech) millimeter-wave network. A real-time algorithm is developed for estimating the rain rate from attenuation using both ITU-R relationships and new coefficients that consider the effects of the rain Drop Size Distribution (DSD). The suggested procedure is tested on measured data, and its performance is evaluated. The results show that the proposed algorithm yields estimates that agree very well with rain gauge data.

Subcarrier mapping (SCM) is considered to be crucial for capacity-maximization in orthogonal frequency division multiplexing (OFDM) relaying networks and has been investigated extensively. However, no study has examined its exact or approximate close-form analysis under Nakagami-m fading. This paper considers the ordered subcarrier pairing schemes, i.e., worst-to-best (WTB) SCM and best-to-best (BTB) SCM, for the analysis of bit error rate (BER) and capacity of a dual-hop OFDM amplify-and-forward (AF) relay system. The system-analysis is presented for Nakagami-m fading with emphasis on two special cases: one-sided Gaussian fading ($(m=rac{1}{2})$) and Rayleigh fading (m=1). Close-form expressions for the probability density function (PDF) and moment generating function (MGF) of end-to-end SNR are derived while considering fixed gain AF relays. The classical MGF and PDF based approaches are used to compare the BER performance of the system with WTB SCM and BTB SCM schemes. Close-form expressions for the upper bound on ergodic capacity are derived by analyzing Jensen's inequality. Accurate analysis is presented for integer m while the non-integer m values allow the derivations of approximate expressions. The accuracy of the suggested approximation is verified analytically as well as numerically. The simulation results validate the analysis in Nakagami-m fading channel.

This paper presents a novel architecture for a fault-tolerant and dual modular redundancy (DMR) system using a checkpoint recovery approach. The architecture features exploitation of SRAM with simultaneous copy and instantaneous compare function. It can perform low-latency data copying between dual cores. Therefore, it can carry out fast backup and rollback. Furthermore, it can reduce the power consumption during data comparison process compared to the cyclic redundancy check (CRC). Evaluation results show that, compared with the conventional checkpoint/restart DMR, the proposed architecture reduces the cycle overhead by 97.8% and achieves a 3.28% low-latency execution cycle even if a one-time fault occurs when executing the task. The proposed architecture provides high reliability for systems with a real-time requirement.

Radio Frequency based Device-Free Localization (RFDFL) is an emerging localization technique without requirements of attaching any electronic device to a target. The target can be localized by means of measuring the shadowing of received signal strength caused by the target. However, the accuracy of RFDFL deteriorates seriously in environment with WiFi interference. State-of-the-art methods do not efficiently solve this problem. In this paper, we propose a dual-band method to improve the accuracy of RFDFL in environment without/with severe WiFi interference. We introduce an algorithm of fusing dual-band images in order to obtain an enhanced image inferring more precise location and propose a timestamp-based synchronization method to associate the dual-band images to ensure their one-one correspondence. With real-world experiments, we show that our method outperforms traditional single-band localization methods and improves the localization accuracy by up to 40.4% in real indoor environment with high WiFi interference.

In this paper we describe and experimentally validate a dual-band digital predistortion (DPD) model we propose that takes account of the intermodulation and harmonic distortion produced when the center frequencies of input bands have a harmonic relationship. We also describe and experimentally validate our proposed novel dual-band power amplifier (PA) linearization architecture consisting of a single feedback loop employing a dual-band mixer. Experiment results show that the DPD linearization the proposed model provides can compensate for intermodulation and harmonic distortion in a way that the conventional two-dimensional (2-D) DPD approach cannot. The proposed feedback architecture should make it possible to simplify analog-to-digital converter (ADC) design and eliminate the time lag between different feedback paths.

Coarse Grained Reconfigurable Architectures (CGRAs) are promising platform based on its high-performance and low cost. Researchers have developed efficient compilers for mapping compute-intensive applications on CGRA using modulo scheduling. In order to generate loop kernel, every stage of kernel are forced to have the same execution time which is determined by the critical PE. Hence non-critical PEs can decrease the supply voltage according to its slack time. The variable Dual-VDD CGRA incorporates this feature to reduce power consumption. Previous work mainly focuses on calculating a global optimal VDDL using overall optimization method that does not fully exploit the flexibility of architecture. In this brief, we adopt variable optimal VDDL in each stage of kernel concerning their pattern respectively instead of the fixed simulated global optimal VDDL. Experiment shows our proposed heuristic approach could reduce the power by 27.6% on average without decreasing performance. The compilation time is also acceptable.