In this paper, a novel channel estimation method for time domain synchrotrons orthogonal frequency domain multiplexing (TDS-OFDM) based on training sequence cyclic reconstruction is proposed to eliminate residual inter-block interference (IBI); it estimates the channel impulse response (CIR) in an iterative manner. A simulation and analysis show that the proposed method can effectively perform the channel estimation over long-delay multipath channels with low complexity.

This letter provides a tight upper bound on the bit error rate (BER) over the Nakagami-m fading channel for the dual carrier modulation (DCM) scheme, which is adopted by the multi-band orthogonal frequency division multiplexing (MB-OFDM) ultra-wideband (UWB) system. Its tightness is verified with the existing result for Rayleigh fading channel, i.e., for m=1, which would be also valid for a more general fading environment.

A dual-band patch antenna with a shorting wall and a U-shaped slot is presented in this paper. The shorted-patch is coupled with the aperture slot that is closely placed to the shorting wall for achieving good impedance matching. A U-shaped slot is embedded in the shorted-patch and is located near the radiating edge to yield a dual-band operation. By changing the side slot length of the U-shaped slot, the tunable frequency ratio of the proposed antenna is varied from 1.73 to 2.05.

In this paper, a linear optimization of the dual-tree complex wavelet transform (DTCWT) based on the least squares method is proposed. The proposed method can design efficient DTCWTs by improving the design degrees of freedom and solving the least square solution iteratively. Because the resulting DTCWTs have good approximation accuracy of the half sample delay condition and the stopband attenuation, they provide precise shift-invariance and directionality. Finally, the proposed DTCWTs are evaluated by applying to non-linear approximation and image denoising, and showed their effectiveness, compared with the conventional DTCWTs.

The asymmetrical halo and dual-material gate structure is used in the surrounding-gate metal-oxide-semiconductor field effect transistor (MOSFET) to improve the performance. By treating the device as three surrounding-gate MOSFETs connected in series and maintaining current continuity, a comprehensive drain current model is developed for it. The model incorporates not only channel length modulation and impact ionization effects, but also the influence of doping concentration and vertical electric field distributions. It is concluded that the device exhibits increased current drivability and improved hot carrier reliability. The derived analytical model is verified with numerical simulation.

CMOS SoCs can reduce power consumption while maintaining performance by adopting voltage scaling (VS) technologies. The operating speed of the level converter (LC) strongly affects the effectiveness of VS technologies. However, PVT variations can cause serious problems to the LC, because the state-of-the-art LC designs do not give enough attention to this issue. In this work, we proposed to analyze the impact of PVT variations on the performance of the LC using a previously developed heuristic sizing methodology. Based on the evaluation results from different operating corners with different offset voltages and temperatures, we proposed a variation-tolerant LC that achieves both high performance and low energy with a high tolerability for PVT variations.

We report on the fabrication of coplanar dual-gate ZnO thin-film transistors with 200-nm thickness SiNx for both top and bottom dielectrics. The ZnO film was deposited by RF magnetron sputtering on SiO2/Si substrates at 100. And the thickness of ZnO film is compared with 100-nm and 40-nm. This TFT has a channel width of 100-µm and channel length of 5-µm. The fabricated coplanar dual-gate ZnO TFTs of 40-nm-thickness exhibits a field effect mobility of about 0.29 cm2/V s, a subthreshold swing 420 mV/decade, an on-off ratio 2.7107, and a threshold voltage 0.9 V, which are greatly improved characteristics, compared with conventional bottom-gate ZnO TFTs.

This paper discusses a dual-stage detection scheme composed of coarse detection stage and refined detection stage for the continuous detection operation of Ultra-Wideband (UWB) detect and avoid (DAA). The threshold factor for the probability of indefinite detection is first proposed and defined to combine the two stages. The proposed scheme focuses on the integration of two different detection schemes with different complexities in order to reduce total computational complexity. A Single-carrier Frequency Division Multiple Access (SC-FDMA) uplink system operating in a Time Division Duplex (TDD) mode is utilized to evaluate the proposed detection scheme. Simulation results indicate that the proposed scheme can make a tradeoff between the detection performance and the computational complexity by setting the probability of indefinite detection.

The adjustable range on post-fabrication resonance wavelength trimming of long-period fiber gratings was broadened toward the blue side, and the mechanisms of the resonance wavelength shifts caused by heating were investigated. It can be concluded that the glass structure relaxes more slowly than the residual stress with decreasing heating temperature and the blue shift caused by the residual stress relaxation appears more strongly at the early stage of heating. The blue shift of 41 nm was obtained by heating a long-period grating at 600 for 3500 minutes. The changes of the index difference inducing the wavelength shifts of -41 nm and 35 nm were estimated at about -1.210-4 and +1.0 10-4 by numerical analysis, respectively.

This letter presents an experiment for estimating accurate state in distributed power systems. This letter employs a technique that combines a projected Jacobi method with a parallel dual-type method to solve the distributed state estimation with constraints problems. Via numerous tests, this letter demonstrates the efficiency of the proposed method on the IEEE 118-bus with four subsystems in a PC network.

This paper presents a syntax-based framework for gap resolution in analytic languages. CCG, reputable for dealing with deletion under coordination, is extended with a memory mechanism similar to the slot-and-filler mechanism, resulting in a wider coverage of syntactic gaps patterns. Though our grammar formalism is more expressive than the canonical CCG, its generative power is bounded by Partially Linear Indexed Grammar. Despite the spurious ambiguity originated from the memory mechanism, we also show that its probabilistic parsing is feasible by using the dual decomposition algorithm.

In this paper, an efficient encoding scheme for dual-diagonal LDPC codes is proposed. Our two-way parity bit correction algorithm breaks up the data dependency within the encoding process to achieve higher throughput, lower latency and better hardware utilization. The proposed scheme can be directly applied to dual-diagonal codes without matrix modifications. FPGA encoder prototypes are implemented for IEEE 802.11n and 802.16e codes. Results show that the proposed architecture outperforms in terms of throughput and throughput/area ratio.

This paper evaluates the performance of a pilot-assisted fine carrier frequency offset (CFO) estimation scheme for orthogonal frequency division multiplexing (OFDM) in time-varying channels. An analytical closed-form expression of the mean square error (MSE), of the post-FFT based CFO synchronization scheme, is presented in terms of time-variant fading channels. To verify our analysis in this paper, simulations are carried out within the framework of mobile WiMAX systems.

In this letter, we address a strategy to enhance the signal-to-interference plus noise ratio (SINR) of the worst-case user by using cooperative transmission from a set of geographically separated antennas. Unlike previously reported schemes which are based on either the power control of individual antennas or cooperative orthogonal transmission, the presented strategy utilizes the minimum-mean-squared error (MMSE) filter structure for beamforming, which provides increased robustness to the external interference as well as the background noise at the receiver. By iteratively updating the cooperative transmission beamforming vector and power control (PC), the balanced SINR is obtained for all users, while the transmission power from each antenna also converges to within the constrained value. It is demonstrated that proposed MMSE beamforming significantly outperforms other existing schemes in terms of the achievable minimum SINR.

A Gaussian MIMO broadcast channel (GMBC) models the MIMO transmission of Gaussian signals from a transmitter to one or more receivers. Its capacity region and different precoding schemes for it have been well investigated, especially for the case wherein there are only transmit power constraints. In this paper, a special case of GMBC is investigated, wherein receive power constraints are also included. By imposing receive power constraints, the model, called protected GMBC (PGMBC), can be applied to certain scenarios in spatial spectrum sharing, secretive communications, mesh networks and base station cooperation. The sum capacity, capacity region, and application examples for the PGMBC are discussed in this paper. Sub-optimum precoding algorithms are also proposed for the PGMBC, where standard user precoding techniques are performed over a BC with a modified channel, which we refer to as the "protection-implied BC." In the protection-implied BC, the receiver protection constraints have been implied in the channel, which means that by satisfying the transmit power constraints on the protection implied channel, receiver protection constraints are guaranteed to be met. Any standard single-user or multi-user MIMO precoding scheme may then be performed on the protection-implied channel. When SINR-matching duality-based precoding is applied on the protection-implied channel, sum-capacity under full protection constraints (zero receive power), and near-sum-capacity under partial protection constraints (limited non-zero receive power) are achieved, and were verified by simulations.

This letter examines the problem of allocating the subcarrier power of the relayed signal in orthogonal frequency division multiplexing (OFDM) based dual-hop systems in which the relay terminal is operated in an Amplify-and-Forward (AF) mode and the source node transmits its signal with a uniform power distribution. In AF relaying systems, both the modulation order and the error control scheme are fixed at the relay node, and thus the potential for increasing the data rate via a suitable allocation of the subcarrier power at the relay node does not exist. Therefore, this study proposes an alternative subcarrier power allocation scheme in which the objective is to scale the power assigned to each of the relayed signal sub-carriers in such a way as to minimize the equivalent average noise power at the destination terminal.

In this paper, a novel feeding technique is proposed to feed a printed rectangular ring patch antenna that attains high gain in two bands simultaneously. The prototype antenna exhibits good impedance bandwidths satisfying ISM 2.45/5.8 GHz achieving maximum gain of 9.56 and 10.17 dBi, respectively, with a stable radiation pattern.

In this paper, a cost-efficient LDPC decoder for DVB-S2 is presented. Based on the Normalized Min-Sum algorithm and the turbo-decoding message-passing (TDMP) algorithm, a dual line-scan scheduling is proposed to enable hardware reusing. Furthermore, we present the solution to the address conflict issue caused by the characteristic of the parity-check matrix defined by DVB-S2 LDPC codes. Based on SMIC 0.13 µm standard CMOS process, the LDPC decoder has an area of 12.51 mm2. The required operating frequency to meet the throughput requirement of 135 Mbps with maximum iteration number of 30 is 105 MHz. Compared with the latest published DVB-S2 LDPC decoder, the proposed decoder reduces area cost by 34%.

This paper presents an asynchronous FPGA that combines 4-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. 4-phase dual-rail encoding is employed to achieve small area and low power for function units, while LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters and their control circuits are also proposed in transistor-level implementation. The proposed FPGA is designed using the e-Shuttle 65nm CMOS process. Compared to the 4-phase-dual-rail-based FPGA, the throughput is increased by 69% with almost the same transistor count. Compared to the LEDR-based FPGA, the transistor count is reduced by 47% with almost the same throughput. In terms of power consumption, the proposed FPGA achieves the lowest power compared to the 4-phase-dual-rail-based and the LEDR-based FPGAs. Compared to the synchronous FPGA, the proposed FPGA has lower power consumption when the workload is below 35%.

We report on the first terahertz emission from a novel dual grating gate plasmon-resonant emitter fabricated with InAlAs/InGaAs/InP material systems. The introduction of InP based heterostructure material systems, instead of the GaAs based ones, in order to improve the quality factor, has successfully enhanced the THz emission intensity and realized the spectral narrowing at room temperature.