In this letter, some more concrete trellis relations between a lattice and its dual lattice are firstly given. Based on these relations, we generalize the main results of [1].

DualFS is a next-generation journaling file system which has the same consistency guaranties as traditional journaling file systems but better performance. This paper introduces three new enhancements which significantly improve DualFS performance during normal operation, and presents different experimental results which compare DualFS and other traditional file systems, namely, Ext2, Ext3, XFS, JFS, and ReiserFS. The experiments carried out prove, for the first time, that a new file system design based on separation of data and metadata can significantly improve file systems' performance without requiring several storage devices.

In this paper, the optimal assignment problem which assigns cells in PCS (Personal Communication Service) to switches on ATM (Asynchronous Transfer Mode) network is investigated. The cost considered in this paper has two components: one is the cost of handoff that involves two switches, and the other is the cost of cabling. This problem assumes that each cell in PCS can be assigned to two switches in ATM network. This problem is modelled as dual-homing cell assignment problem, which is a complex integral linear programming (ILP) problem. Since finding an optimal solution of this problem is NP-hard, a hybrid method which combines several heuristics and a stochastic search method (based on a simulated annealing(SA) approach) is proposed to solve this problem. The solution method consists of three phases: Primary Assignment Decision Phase (PADP), Secondary Assignment Decision Phase (SADP) and Refinement Phase (RP). The PADP and SADP are used to find good initial assignment, then domain-dependent heuristics are encoded into perturbations of SA in Refinement Phase to improve the result. Simulation results show that the proposed hybrid method is robust for this problem.

This paper presents a new high-speed and area-efficient dual-rail PLA. The proposed circuit includes three schemes: 1) a divided column scheme (DCS), 2) a programmable sense-amplifier activation scheme (PSAS), and 3) an interdigitated column scheme (ICS). In the DCS, a column circuit of a PLA is divided and each circuit operates in parallel. This enhances the performance of the PLA, and this scheme becomes more effective as input data bandwidth increases. The PSAS is used to generate an activation pulse for sense amplifiers in the PLA. In this scheme, the proposed delay generators enable to minimize a timing margin depending on process variations and operating conditions. The ICS is used to enhance the area-efficiency of the PLA, where a method of physical compaction is employed. This scheme is effective for circuits which have the regularity in logic function such as arithmetic circuits. As applications of the proposed PLA, a comparator, a priority encoder, and an incrementor for 128-bit data processing were designed. The proposed circuit design schemes achieved a 22.2% delay reduction and a 37.5% area reduction on average over the conventional high-speed and low-power PLA in a 0.13-µm CMOS technology with a supply voltage of 1.2 V.

This paper presents a network architecture with a dual interface IP handoff technique that allows smooth node mobility without using any intermediate proxy. The proposed architecture is suitable for low bit-rate time sensitive real time applications, where payload tends to be short and packet header overhead is particularly significant. Connections are established as per permanent addresses of the nodes but are carried on by the IP layer according to the temporary addresses by address translation within the end hosts. The mapping information is maintained by database servers, which can be placed in the Internet in a distributed manner. We describe the architecture and show its mobile capabilities by prototype implementation and performance evaluation. Furthermore a dual-interface handoff suitable to the proposed architecture is also introduced. Preliminary results show that the proposed architecture has significantly low overheads. It is compatible with the existing infrastructure and works fine in both IPv4 and IPv6 environments. Analysis also shows that with dual-interface handoff it is possible to achieve seamless handoff without any packet loss by exploiting overlapping coverage area and speed of the mobile node. Handoff latency is reduced significantly as compare to MIPv6. We believe that with more powerful network interface card drivers our concept of dual interface handoff can be realized.

This paper addresses the problem of arranging fewest possible probes to detect a hidden object in a specified region and presents a reasonable scheme for the purpose. Of special interest is the case where an object is a double-sided conic cylinder which represents the shape of the energy distribution of laser light used in the optical network. The performance of our scheme is evaluated by comparing the number of probes to that of an existing scheme, and our scheme shows a potential for reducing the number of probes. In other words, the time for detection is significantly reduced from a realistic point of view.

We consider a new post-filtering algorithm for residual acoustic echo cancellation in hands-free application. The new post-filtering algorithm is composed of AR analysis, pitch prediction, and noise reduction algorithm. The residual acoustic echo is whitened via AR analysis and pitch prediction during no near-end talker period and then is cancelled by noise reduction algorithm. By removing speech characteristics of the residual acoustic echo, noise reduction algorithm reduces the power of the residual acoustic echo as well as the ambient noise. For the hands-free application in the moving car, the proposed system attenuated the interferences more than 15 dB at a constant speed of 80 km/h.

In low-power embedded processors design, stand-by power constraint is also important with average power and operation frequency. Multi-threshold-voltage cells are used in the design and the ratio of low-Vth cells should be controlled. On the other hand, physical synthesis flow is indispensable to achieve high performance and short design time. This paper proposes a physical synthesis methodology under the restriction of maximum low-Vth cell ratio. The experimental results show that our method can achieve only 4 MHz slower logic within 5% margin of the target low-Vth ratio. We have applied this design flow in an application processor design and the designed processor demonstrates 360 MIPS at 200 MHz only with 80 mW at 1.0 V, namely 4500 MIPS/W and 4.2 mA leakage current without any power-cut mode.

A compact wide-band antennas design for the 2.4 GHz/5.8 GHz dual ISM-band application is introduced by combing a single-feed and single-layer microstrip antenna in the form of a T-type strip with an edge perturbation. Good impedance bandwidth performance for the dual-band is observed. The advantage of the design suggested in this paper is its simplicity of manufacturing and low cost.

This paper describes an area-efficient dual-rail array logic architecture, a logic-cell-embedded PLA (LCPLA), which has 2-input logic cells in the structure. The 2-input logic cells composed of pass-transistors can realize any 2-input Boolean function and are embedded in a dual-rail PLA. The logic cells can be designed by connecting some local wires and do not require additional transistors over logic cells of the conventional dual-rail PLA. By using the logic cells, some classes of logic functions can be implemented efficiently, so that high-speed and low-power operations are also achieved. The advantages over the conventional PLAs and standard-cell-based designs were demonstrated by using benchmark circuits, and the LCPLA is shown to be effective to reduce the number of product terms. In a structure with a 64-bit input and a 1-bit output including 220 product terms, the LCPLA achieved an area reduction by 35% compared to the conventional high-speed dual-rail PLA, and the power-delay product was reduced by 74% and 46% compared to the conventional high-speed single-rail PLA and the conventional high-speed dual-rail PLA, respectively. A test chip of this configuration was fabricated using a 0.35-µm, 3-metal-layer CMOS technology, and was verified with a functional test using a logic tester and an electron-beam tester at frequencies of up to 100 MHz with a supply voltage of 3.3 V.

This work presents a new sigma-delta modulator (SDM) architecture for a wide bandwidth receiver. This architecture contains dual-bandwidth for W-CDMA and GSM system applications. Low-distortion swing-suppressing SDM and interpolative SDM cascaded units are used together. Using the low-distortion swing-suppressing technique, the resolution can be improved even under non-linearity effects. The interpolative SDM extends the signal bandwidth and represses the high-band noise. The SDM used in the W-CDMA and GSM applications was designed and simulated using 0.25-µm 1P5M CMOS technology. The simulated peak SNDR of W-CDMA and GSM are 72/70 dB and 82/84 dB in Low-IF/Zero-IF standards.

The present paper reports a robust projection onto eigenspace that is based on iterative projection. The fundamental method proposed in Shakunaga and Sakaue and involves iterative analysis of relative residual and projection. The present paper refines the projection method by solving linear equations while taking noise ratio into account. The refinement improves both the efficiency and robustness of the projection. Experimental results indicate that the proposed method works well for various kinds of noise, including shadows, reflections and occlusions. The proposed method can be applied to a wide variety of computer vision problems, which include object/face recognition and image-based rendering.

In this letter, we present groupwise successive interference cancellation (GSIC) receiver with adaptive minimum mean squared error (MMSE) detection and extended GSIC (EGSIC) receiver with adaptive MMSE detection for dual-rate DS-CDMA system. The receivers are GSIC receiver and EGSIC receiver combined with adaptive MMSE detection which is introduced to make initial bit detection more reliable. Furthermore, a multi-user detection scheme is introduced to mitigate the effect of multiple access interference (MAI) between users in a group which is usually ignored in conventional GSIC receiver and EGSIC receiver. Specifically, parallel interference cancellation (PIC) is adopted as a multi-user detection scheme within a group. It is shown that performance of the GSIC receiver and EGSIC receiver is significantly improved by employing adaptive MMSE detection. It is also shown that the performance of the receivers can be improved further by using PIC within a group.

The dense wavelength division multiplexing (DWDM) technique is very attractive for effectively increasing the channel capability, even for access networks. Some DWDM radio-on-fiber (ROF) systems have been studied recently. In those systems, fiber Bragg gratings (FBG) or arrayed waveguide gratings (AWG) were used to demultiplex DWDM ROF signals. In this report, an alternative channel-selection scheme of DWDM millimeter-wave-band ROF signals by optical heterodyne detection with dual-mode local light is newly proposed. Error-free demultiplexing and transmission over a 25-km-long SMF of the DWDM signal, which consists of two 60-GHz-band, 155-Mb/s-DPSK ROF signals, are demonstrated.

A novel optical modulation scheme is proposed for synthesizing a pair of dual-mode optical BPSK signals with an orthogonal phase relationship via a LiNbO3 Mach-Zehnder modulator (MZM) with dual RF signal inputs and a carrier suppression feature, which enables the generation of a crosstalk-free QPSK signal at the photodetection stage. With this method, one can compensate the drawback, that is bandwidth broadening, in our previously proposed method where a dual-mode optical QPSK signal is generated on the basis of narrow-angle modulated QPSK signal injection into a double-sideband suppressed carrier MZM device. We have carried out experiments for 60 GHz performance demonstration of this QPSK signal generation mechanism, and the results indicate the effectiveness of the present scheme.

The paper presents a dual-band switchable low noise amplifier implemented in 0.25-µm CMOS technology for 5-GHz wireless multimedia applications. The high-speed wireless multimedia applications call for broadband design techniques for RF circuits. Instead of using conventional broadband techniques not well suitable for CMOS implementation, a dual-band switchable load is proposed for broadband LNA design. The dual-band switchable load enables the LNA operate at the lower or the upper band at 5-GHz band by a 1-bit control signal. The LNA exhibits over 17 dB power gain, 3.5 dB noise figure and input 1-dB compression point -23 dBm in both frequency bands. It draws 9.5 mA from 2.5 V supply. The power gain remains larger than 16 dB as temperature varies from -5 to 65.

In this paper, a novel direct torque control (DTC) for a dual-three-phase induction motor(DTPIM) is presented. A rule-based optimum selection scheme for the space voltage vector is proposed. A fast torque response with low ripples of torque and flux is achieved. To further reduce the ripple of torque and stator flux, a fuzzy logic estimator for the duty ratio is developed, so that the average effective voltage on the motor can be flexibly changed within the sampling period. The simulation results clearly demonstrate precise control of the stator flux and torque with the new DTC method and a better steady state performance with the proposed fuzzy logic technique.

A dual-polarized multimode CDMA based local multipoint distribution system (LMDS) is presented. The twisted sector concept and narrowed sector cell are proposed to improve the system performance. Inter-cell interference is analyzed and discussed for the downstream direction based on hexagonal cell architecture. The bit error rate (BER) performance of a multimode CDMA scheme is investigated in terms of the worst case for high order modulation. The simulation results show that the proposed cell structure obtains better power efficiency and makes the multimode CDMA scheme feasible in LMDS deployment.

The adaptive phase tracking scheme for orthogonal frequency division multiplexing (OFDM) signals can provide superior PER performance in channels with varying phase noise power. It is an effective technique for achieving high-rate and high quality wireless transmission. This paper proposes a new simple adaptive phase tracking scheme for OFDM signals in order to realize high-rate wireless local area networks (LANs). The proposed scheme measures the integrated phase rotation in order to appropriately set the properties of the FIR filter in the phase tracking circuits. This scheme uses the fact that the integrated phase rotation is correlated to the phase noise power. Assuming an RMS delay spread of 100 ns, computer simulations show that the proposed scheme offers superior required Eb/N0 performance (with regard to the phase noise power) compared to the conventional fixed-tap scheme, where the phase noise to signal power ratios are below -18 dB. It also offers excellent PER performance at the packet length of 1000 bytes unlike the conventional schemes, which suffer degraded PER performance.

A wireless communications system with a transmission speed of 18 Mbit/s is presented using the 2.4 GHz ISM band. This system employs the Carrier Frequency Offset-Spread Spectrum (CFO-SS) scheme and the Dual-Polarization Staggered Transmission (DPST) scheme. The 18 Mbit/s CFO-SS system (named CFO-SS18) was developed and its performance evaluated in fields. In this paper, the detailed operating principle of CFO-SS and DPST schemes, together with the specifications and structures of CFO-SS18, are presented. Results of indoor and field tests obtained by using CFO-SS18 are also presented.