Topology information has become more important for management of LANs due to the increasing number of hosts attached to a LAN. We describe three Ethernet topology discovery techniques that can be used even in LANs with Ethernet switches that have no management functionality. Our "Shared Switch Detection (SSD)" technique detects the Ethernet tree topology by testing whether two paths in the network share a switch. SSD uses only general MAC address learning. By borrowing MAC addresses from hosts, SSD can be run from a single host. The second technique determines whether two paths between two pairs of hosts contain a switch. The third reduces the number of shared switch detections. Simulation showed that these techniques can be used to detect the Ethernet topology with a reasonable search cost. Examination on a real-world testbed showed that they could detect an Ethernet topology consisting of six hosts and two switches within one second.

Frame loss of the optical layer protection switching using Plumbum Lanthanum Zirconium Titanium (PLZT) optical switch is evaluated. Experimental results show that typically 62 µs guard time is required for commercially available non-burst mode 10 Gigabit Ethernet modules.

We present a recovery scheme based on Self-protected Spanning Tree (SST), which recovers from failure all by itself. In the recovery scheme, the links are assigned birthdays to denote the order in which they are to be considered for adding to the SST. The recovery mechanism, named Birthday-based Link Replacing Mechanism (BLRM), is able to transform a SST into a new spanning tree by replacing some tree links with some non-tree links of the same birthday, which ensures the network connectivity after any single link or node failure. First, we theoretically prove that the SST-based recovery scheme can be applied to arbitrary two-edge connected or two connected networks. Then, the recovery time of BLRM is analyzed and evaluated using Ethernet, and the simulation results demonstrate the effectiveness of BLRM in achieving fast recovery. Also, we point out that BLRM provides a novel load balancing mechanism by fast changing the topology of the SST.

A fast class-of-service oriented packet scheduling (FCOPS) has a service fairness problem since a credit pool for a service class is initialized at the beginning of a transmission cycle whose starting moment is fixed at a specific ONU. To remedy the service unfairness of FCOPS, we suggest an enhanced class-of-service oriented packet scheduling (ECOPS) that uses a new initialization cycle whose starting moment is fairly distributed to each ONU. Also, ECOPS generates a colorless grant to utilize the resource wastage, when traffic is light and the total sum of grants of an ONU is less than a minimum size. Using simulation, we validate ECOPS as superior to FCOPS in the mean delay and the service fairness.

We developed a 44 SFQ network switch prototype system and demonstrated its operation at 10 Gbps. The system's core is composed of two SFQ chips: a 44 switch and a 6-channel voltage driver. The 44 switch chip contained both a switch fabric (i.e. a data path) and a switch scheduler (i.e. a controller). Both chips were attached to a multi-chip-module (MCM) carrier, which was then installed in a cryocooled system with 32 10-Gbps ports. Each chip contained about 2100 Josephson junctions on a 5-mm5-mm die. An NEC standard 2.5-kA/cm2 fabrication process was used for the switch chip. We increased the critical current density to 10 kA/cm2 for the driver chip to improve speed while maintaining wide bias margins. MCM implementation enabled us to use a hybrid critical current density technology. Voltage pulses were transferred between two chips through passive transmission lines on the MCM carrier. The cryocooled system was cooled down to about 4 K using a two-stage 1-W cryocooler. We correctly operated the whole system at 10 Gbps. The switch scheduler, which is driven by an on-chip clock generator, operated at 40 GHz. The speed gap between SFQ and room temperature devices was filled by on-chip SFQ FIFO buffers or shift registers. We measured the bit error rate at 10 Gbps and found that it was on the order of 10-13 for the 44 SFQ switch fabric. In addition, using semiconductor interface circuitry, we built a four-port SFQ Ethernet switch. All the components except for a compressor were installed in a standard 19-inch rack, filling a space 21 U (933.5 mm or 36.75 inches) in height. After four personal computers (PCs) were connected to the switch, we have successfully transferred video data between them.

We suggest a dual thresholds method for the dynamic bandwidth allocation in EPON. In the suggested method, a buffer in ONU has two thresholds and ONU generates a normal request and a greedy request based on the two thresholds. Also, OLT estimates the overall traffic load and grants the greedy request when estimated traffic is light. We study upstream channel resource wastage and show the suggested method decreases the upstream channel resource wastage. Using simulation, we validate the dual thresholds method is superior to the existing methods in the mean delay.

The present paper describes an implementation of an intrusion detection system (IDS) on an FPGA for 10 Gigabit Ethernet. The system includes an exact string matching circuit for 1,225 Snort rules on a single device. A number of studies have examined string matching circuits for IDS. However, implementing a circuit that processes a large rule set at high throughput is difficult. In a previous study, we proposed a method for generating an NFA-based string matching circuit that has expandability of processing data width and drastically reduced resource requirements. In the present paper, we implement an IDS circuit that processes 1,225 Snort rules at 10 Gbps with a single Xilinx Virtex-II Pro xc2vp-100 using the NFA-based method. The proposed circuit also provides packet filtering for an intrusion protection system (IPS). In addition, we developed a tool for automatically generating the Verilog HDL source code of the IDS circuit from a Snort rule set. Using the FPGA and the IDS circuit generator, the proposed system is able to update the matching rules corresponding to new intrusions and attacks. We implemented the IDS circuit on an FPGA board and evaluated its accuracy and throughput. As a result, we confirmed in a test that the circuit detects attacks perfectly at the wire speed of 10 Gigabit Ethernet.

A high-speed physical-layer architecture for next-generation higher-speed Ethernet for VSR and backplane applications was developed. VSR and backplane networks provide 100-Gb/s data transmission in "mega data centers" and blade servers, which have new and broad potential markets of LAN technologies. It supports 100-Gb/s-throughput, high-reliability, and low-latency data transmission, making it well suited to VSR and backplane applications for intra-building and intra-cabinet networks. Its links comprise ten 10-Gb/s high-speed serial lanes. Payload data are transmitted by ribbon fiber cables for very short reach and by copper channels for the backplane board. Ten lanes convey 320-bit data synchronously (32 bits10 lanes) and parity data of forward-error correction code (newly developed (544, 512) code FEC), providing highly reliable (BER<1E-22) data transmission with a burst-error correction with low latency (31.0 ns on the transmitter (Tx) side and 111.6 ns on the receiver (Rx) side). A 64B/66B code-sequence-based skew compensation mechanism, which provides low-latency compensation for the lane-to-lane skew (less than 51 ns), is used for parallel transmission. Testing this physical-layer architecture in an ASIC showed that it can provide 100-Gb/s data transmission with a 772-kgate circuit, which is small enough for implementation in a single LSI.

In this paper, we examine the Interleaved Polling with Adaptive Cycle Time (IPACT) that was proposed to control upstream traffic for Gigabit Ethernet-PONs, a promising technology for the Fiber To The Home (FTTH). We analyzed the performance for the gated service and the limited service mathematically. To do this, the IPACT protocol was modeled as a polling system and analyzed by using mean-value analysis technique. The traffic arrival rate λ was divided into three regions, and each region was analyzed separately and merged appropriately by using an interpolation method. The average packet delay, average queue size, and average cycle time of both the gated service and the limited service were obtained through the analysis. In order to evaluate the accuracy of the mathematical analysis, discrete event simulation was performed for the IPACT protocol. Simulation results show the accuracy of the mathematical analysis. The analysis results can be widely used in the design of the FTTH system based on EPON, as the performance results in the present study can be obtained in a rather short time. We can design an appropriate system depending on various traffic conditions by adjusting system parameters, such as the number of users N, the maximum transfer window WMAX, and so on.

We suggest a new minimum credit method for the dynamic bandwidth allocation in EPON. In the suggested method, to eliminate the unused transmission time-slot, each ONU requests no more than a predetermined maximum. We analyze the upstream channel resource wastage when traffic is light. Based on the analysis, we derive a minimum credit that eliminate the upstream channel resource wastage. The OLT estimates a traffic load and grants a minimum credit when the request is smaller than the minimum credit and traffic is light. Using simulation, we show the minimum credit discipline is superior than the existing methods in the mean delay and the frame loss rate.

A novel cache-based network processor (NP) architecture that can catch up with next generation 100-Gbps packet-processing throughput by exploiting a nature of network traffic is proposed, and the prototype is evaluated with real network traffic traces. This architecture consists of several small processing units (PUs) and a bit-stream manipulation hardware called a burst-stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC) and a cache-miss handler (CMH). The PLC memorizes a packet-processing method with all table-lookup results, and applies it to subsequent packets that have the same information in their header. To avoid packet-processing blocking, the CMH handles cache-miss packets while registration processing is performed at the PLC. The combination of the PLC and CMH enables most packets to skip the execution at the PUs, which dissipate huge power in conventional NPs. We evaluated an FPGA-based prototype with real core network traffic traces of a WIDE backbone router. From the experimental results, we observed a special case where the packet of minimum size appeared in large quantities, and the cache-based NP was able to achieve 100% throughput with only the 10%-throughput PUs due to the existence of very high temporal locality of network traffic. From the whole results, the cache-based NP would be able to achieve 100-Gbps throughput by using 10- to 40-Gbps throughput PUs. The power consumption of the cache-based NP, which consists of 40-Gbps throughput PUs, is estimated to be only 44.7% that of a conventional NP.

This paper shows the recent standardization activities on Ethernet OAM functions. First, it briefly introduces recent carrier class Ethernet services indicating their characteristics and operational issues. Then, it explains current standardization status on Ethernet OAM functions. Finally it shows the requirements for Ethernet OAM functions and details of the OAM mechanisms currently being standardized by ITU-T SG13, SG15 and IEEE 802.1 WG.

A high-speed physical-layer architecture for Ethernet is described that supports 100-Gb/s throughput and 40-km transmission, making it well suited for next-generation metro-area and intrabuilding networks. Its links comprise 1210-Gb/s synchronized parallel optical lanes. Ethernet data frames are transmitted by coarse wavelength division multiplexing link and bundled optical fibers. Ten of the lanes convey 640-bit data synchronously (64 bits10 lanes). One conveys forward error correction code ((132 b, 140 b) Hamming code), providing highly reliable (BER < 10-12) data transmission, and the other conveys parity data, enabling fault-lane recovery. A newly developed 64B/66B code-sequence-based deskewing mechanism is used that provides low-latency compensation for the lane-to-lane skew, which is less than 88 ns. Testing of this physical-layer architecture in a field programmable gate array circuit demonstrated that it can provide 100-Gb/s data communication with a 590 k gate circuit, which is small enough for implementation in a single LSI circuit.

The Ethernet network is widely used and adopted to the access portion or metro area for the reason of new applications for native Ethernet services or its economical advantage. Apart from these applications for native Ethernet, an encapsulation technology to transport legacy services over Ethernet, i.e. TDM over Ethernet, is focused on. In order to apply it to the carrier networks, it is necessary to meet Quality of Service (QoS) requirements, and the consideration of operation, administration and maintenance (OAM) aspects are indispensable. Furthermore, in order for higher reliability, it is required to apply protection function to the networks. We have studied the encapsulation method of TDM signals applied to circuit emulator accommodating TDM signals over Ethernet. In addition, the OAM mechanism and the protection function are studied. This paper shows the frame format, the detail of the OAM mechanism and the protection function, and introduces a developed circuit for adaptation of TDM over Ethernet.

Time synchronization is indispensable for wide area distributed systems including sensor networks, automation systems, and measurement/control systems. Another application is clock distribution, which is indispensable to support continuous information transfer. Because of the increasing demand for more sophisticated applications, it is essential to establish a time synchronization technique that offers higher accuracy and reliability. Particularly, the accuracy of time synchronization for Ethernet must be enhanced since Ethernet is becoming more important in telecommunication networks. This paper investigates a precise time synchronization technique that supports Gb/s Ethernet. To obtain accurate time synchronization, delay variation in message transfer and processing must be minimized. For this purpose, the paper first describes the implementation of preemptive priority queuing, which decreases the message delay variation of Ethernet. Through experiments, it is shown that preemptive priority queuing effectively achieves very low delay variation. The paper then proposes a method to synchronize the time signal of a slave node to that of the master node. The proposed time synchronization method is performed in the lower protocol layer and implemented on FPGA-based hardware. The method achieves superior time accuracy through the low message transfer/processing delay variation provided by preemptive priority, lower layer execution, and hardware implementation. The effectiveness of the method is confirmed through experiments. The experiments show that the time variation achieved by the method is smaller than 0.1 µsec. This performance is better than those obtained by existing synchronization methods.

In this paper, authors present new schemes of our proposed Global Open Ethernet (GOE) technology from a viewpoint of improving reliability in metro-area Ethernet environment and show the numerical evidence on their performance results. Although several standardized or vendor proprietary technologies are proposed to improve Ethernet reliability, they still have reliability problems in terms of long failure recovery time (due to forwarding database (FDB) flush and recovery from a root bridge failure on spanning tree protocol), broadcast storm, and packet loss in network reconfiguration. To solve these problems, we introduce three schemes, a Per Destination - Multiple Rapid Spanning Tree Protocol (PD-MRSTP), a GOE Virtual Switch Redundancy Protocol (GVSRP), and an In-Service Reconfiguration (ISR) schemes. PD-MRSTP scheme reduces the failure recovery time by eliminating the need to flush the FDB and to recover from root bridge failures. GVSRP scheme ensures the reliability of connections between a GOE domain and a legacy Ethernet domain. Combined with PD-MRSTP, GVSRP prevents broadcast storm problems due to loops in the inter-domain area. ISR scheme enables in-service bridge replacement and upgrade without packet loss. Evaluating our prototype system, we obtained the following remarkable performance results. The GOE network using PD-MRSTP scheme delivered a fast failure recovery performance (4 ms) independent of the number of MAC address entries, whereas the legacy Ethernet network took 522 ms when a bridge had 6000 MAC address entries. Since we found that the failure recovery time increased in proportion to the number of MAC address entries, the one in large carrier network having one million of MAC address entries would take several tens of seconds. Thus using PD-MRSTP can reduce failure recovery time one ten-thousandth comparing with that of legacy Ethernet. In addition, evaluation of the ISR scheme demonstrated that a network can be upgraded with zero packet loss. Therefore, a GOE-based VPN is a promising alternative to other Ethernet VPNs for its reliability and stability.

A significant growth in FTTH access rates has been seen in the last year. This paper overviews the deployed FTTH access systems and the recent application of Ethernet technologies. The standardization activities and further study issues are also discussed.

This paper describes an overview of overall carrier-grade Ethernet technologies for next generation wide area Ethernet. In recent years, from access network to metro and core network, we can find many areas where communication services are provided by Ethernet technologies. This comes from the fact that operational efficiency and economical efficiency of Ethernet are far better than that of conventional wide area communication technologies such as SONET and ATM. On the other hand, carrier-grade reliability, operations-administration-maintenance (OAM) and quality of service (QoS) are inferior to SONET and ATM. Various standard schemes in IEEE 802 and ITU-T and vendors' proprietary schemes can leave various approaches to solve these problems. In this paper, the author explains a basic architecture of wide area Ethernet service (Q-in-Q tagging for metro network and Mac-in-Mac encapsulation for core network) at first. Various switch control technologies are then discussed which are deployed or are under evaluation in order to improve (i) reliability (i.e., resiliency) to protect subscribers against network failures, (ii) OAM for providers to perform fault and performance management, and (iii) QoS to guarantee subscriber's service level agreement between a carrier and a subscriber. Finally, a new switching architecture, Global Open Ethernet (GOE), is also introduced as one of promising approaches to realize a next generation carrier-grade Ethernet.

As an alternative solution to provide the quality of services (QoS) for broadband access over Ethernet Passive Optical Network (EPON), we present the usage of MAC control message for plural class queues and a traffic-class burst-polling based delta dynamic bandwidth allocation (DBA), referred to as TCBP-DDBA, scheme. For better QoS support, the TCBP-DDBA minimizes packet delays and delay variations for expedited forwarding packet and maximizes throughput for assured forwarding and best effort packets. The network resources are efficiently utilized and adaptively allocated to the three traffic classes for the given unbalanced traffic conditions by guaranteeing the requested QoS. Simulation results using OPNET show that the TCBP-DDBA scheme performs well in comparison to the conventional unit-based allocation scheme over the measurement parameters such as: packet delay, packet delay variation, and channel utilization.

Given the availability of high-speed Ethernet and HW based protocol offload, clustered systems using a commodity network fabric (e.g., TCP/IP over Ethernet) are expected to become more attractive for a range of e-business and data center applications. In this paper, we describe a comprehensive simulation to study the performance of clustered database systems using such a fabric. The simulation model currently supports both TCP and SCTP as the transport protocol and models an Oracle 9i like clustered DBMS running a TPC-C like workload. The model can be used to study a wide variety of issues regarding the performance of clustered DBMS systems including the impact of enhancements to network layers (transport, IP, MAC), QoS mechanisms or latency improvements, and cluster-wide power control issues.