In this research, we investigated the threshold voltage (VTH) control by partial polarization of metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) with 5 nm-thick nondoped HfO2 gate insulator utilizing Kr-plasma sputtering for Pt gate electrode deposition. The remnant polarization (2Pr) of 7.2 μC/cm2 was realized by Kr-plasma sputtering for Pt gate electrode deposition. The memory window (MW) of 0.58 V was realized by the pulse amplitude and width of -5/5 V, 100 ms. Furthermore, the VTH of MFSFET was controllable by program/erase (P/E) input pulse even with the pulse width below 100 ns which may be caused by the reduction of leakage current with decreasing plasma damage.

In this research, we investigated the metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) with 5nm thick nondoped HfO2 gate insulator by decreasing the sputtering power for Pt gate electrode deposition. The leakage current was effectively reduced to 2.6×10-8A/cm2 at the voltage of -1.5V by the sputtering power of 40W for Pt electrode deposition. Furthermore, the memory window (MW) of 0.53V and retention time over 10 years were realized.

In this research, we investigated the effect of Hf inter layer and chemical oxide on Si(100) substrate on the ferroelectric undoped HfO2 deposition. In case with 1 nm-thick Hf inter layer, equivalent oxide thickness (EOT) was decreased from 6.0 to 4.8 nm for 10 nm-thick HfO2 with decreasing annealing temperature. In case with 0.5 nm-thick chemical oxide, EOT was decreased from 3.9 to 3.6 nm in MFS diodes for 5 nm-thick HfO2. The MFSFET was fabricated with 10 nm-thick HfO2 utilizing Hf inter layer. The subthreshold swing was improved from 240 mV/dec. to 120 mV/dec. and saturation mobility was increased from 70 cm2/(Vs) to 140 cm2/(Vs) by inserting Hf inter layer.

Ferroelectric gate field-effect transistors (MFSFETs) were investigated utilizing nondoped HfO2 deposited by RF magnetron sputtering utilizing Hf target. After the post-metallization annealing (PMA) process with Pt top gate at 500°C/30s, ferroelectric characteristic of 10nm thick nondoped HfO2 was obtained. The fabricated MFSFETs showed the memory window of 1.7V when the voltage sweep range was from -3 to 3V.

We have investigated post-metallization annealing (PMA) utilizing TiN gate electrode on the thin ferroelectric undoped HfO2 directly deposited on p-Si(100) by RF magnetron sputtering. By post-deposition annealing (PDA) process at 600°C/30 s in N2, the memory window (MW) in the C-V characteristics was observed in the Al/HfO2/p-Si(100) diodes with 15 to 24-nm-thick HfO2. However, it was not obtained when the thickness of HfO2 was 10 nm. On the other hand, the MW was observed for Pt/TiN/HfO2 (10 nm)/p-Si(100) diodes utilizing PMA process at 600°C/30 s. The MW was 0.5 V when the bias voltage was applied from -3 to 3 V.

We integrate a pressure sensing capacitor and a low operation voltage OFET to develop a pressure sensor. The OFET was used as a readout device and an external pressure was loaded on the sensing capacitor. The OFET operates at less than 5 V and the change in the drain current in response to the pressure load (100 kPa) is two orders of magnitude.

An artificial transmission line with variable capacitors as its shunt elements, also known as a nonlinear transmission line, can be used to generate pulsed waveforms with short durations. In this work, the variable capacitors are implemented using ferroelectric materials. Analysis and experimental results of such a ferroelectric-based artificial transmission line are presented. The differential equation that describes the nonlinear transmission line is derived and solved. The analytical expression for the solitary waves propagating along the line is found. An artificial transmission line is fabricated using thin-film barium--strontium--titanate capacitors and commercially available chip inductors. The fabrication process of the ferroelectric-based artificial transmission line is described. On-wafer characterization of the line is performed. Measurement results show that, with proper dc bias and substantial input power, a sinusoidal input waveform turns into a bell-shaped pulse train at the output, demonstrating the pulse-shaping capability of the ferroelectric-based artificial transmission line.

A ferroelectric-based (FE-based) non-volatile logic is proposed for low-power LSI. Standby currents in a logic circuit can be cut off by using FE-based non-volatile flip-flops (NVFFs), and the standby power can be reduced to zero. The FE capacitor is accessed only when the power turns on/off, performance of the NVFF is almost as same as that of the conventional flip-flop (FF) in a logic operation. The use of complementarily stored data in coupled FE capacitors makes it possible to realize wide read voltage margin, which guarantees 10 years retention at 85 degree Celsius under less than 1.5V operation. The low supply voltage and electro-static discharge (ESD) detection technique prevents data destruction caused by illegal access for the FE capacitor during standby state. Applying the proposed circuitry in CPU, the write and read operation for all FE capacitors in 1.6k-bit NVFFs are performed within 7µs and 3µs with access energy of 23.1nJ and 8.1nJ, respectively, using 130nm CMOS with Pb(Zr,Ti)O3(PZT) thin films.

We fabricated high-quality domain-inverted MgO: LiNbO$_3$ structures with 3.0 and 2.0~$mu$m periods using applying votage to the corrugation electrode. We found that keeping the crystal temperature at 150$^{circ}$C for 12 hours before applying voltage was effective for obtaining good uniformity. We also demonstrated an application of the structures with 3.0~$mu$m period to electro-optic Bragg deflection modulator for the first time.

In this paper, a 60 nm-thick ferroelectric film of poly(vinylidene fluoride–trifluoroethylene) on a flexible substrate of aluminum foil was fabricated and characterized. Compared to pristine silicon wafer, Al-foil has very large root-mean-square (RMS) roughness, thus presenting challenges for the fabrication of flat and uniform electronic devices on such a rough substrate. In particular, RMS roughness affects the leakage current of dielectrics, the uniformity of devices, and the switching time in ferroelectrics. To avoid these kinds of problems, a new thin film fabrication method adopting a detach-and-transfer technique has been developed. Here, 'detach' means that the ferroelectric film is detached from a flat substrate (sacrificial substrate), and 'transfer' refers to the process of the detached film being moved onto the rough substrate (main substrate). To characterize the dielectric property of the transferred film, polarization and voltage relationships were measured, and the results showed that a hysteresis loop could be obtained with low leakage current.

Initialize and weak-program erasing scheme is proposed to achieve high-performance and high-reliability Ferroelectric (Fe-) NAND flash solid-state drive (SSD). Bit-by-bit erase VTH control is achieved by the proposed erasing scheme and history effects in Fe-NAND is also suppressed. History effects change the future erase VTH shift characteristics by the past program voltage. The proposed erasing scheme decreases VTH shift variation due to history effects from ±40% to ±2% and the erase VTH distribution width is reduced from over 0.4 V to 0.045 V. As a result, the read and VPASS disturbance decrease by 42% and 37%, respectively. The proposed erasing scheme is immune to VTH variations and voltage stress. The proposed erasing scheme also suppresses the power and bandwidth degradation of SSD.

This paper presents an improvement of the memory cell reliability by the memory cell VTH optimization of the ferroelectric (Fe)-NAND flash memory. The effects of the memory cell VTH on the reliability of the Fe-NAND flash memory are experimentally analyzed for the first time. The reliability is evaluated by the measured VTH shift due to the read disturb, program disturb and data retention. Three types of Fe-NAND flash memory cells, a positive, zero and negative VTH memory cell, are defined on the basis of the memory cell VTH. The middle of VTH of programmed and erased states is 1 V, 0 V and -0.3 V in a positive, zero and negative VTH memory cell, respectively. The VTH shift of the positive, zero and negative VTH memory cells show similar characteristics in the program/erase and the VPASS and VPGM disturbs because the external electric field is so high that the internal depolarization field does not affect the VTH shift. On the other hand, in the data retention, the VTH shift of the three types of VTH memory cells show different characteristics. The reliability of the Fe-NAND flash memory is best optimized in the zero VTH memory cell. In the proposed zero VTH Fe-NAND flash memory cell scheme, the measured VTH shift due to the read disturb, program disturb and data retention decreases by 32%, 24% and 10%, respectively, compared with conventional positive VTH Fe-NAND flash memory cell scheme. Contrarily, in the negative VTH memory cell, the VTH shift during the data retention is 0.49 V and unacceptably large because of the depolarization field. The conventional positive VTH memory cell suffers from a sever read and program disturb. The measured results are drastically different from those of the conventional floating-gate NAND flash memory cell where the negative VTH memory cell is most suitable in terms of the reliability.

This paper investigates intermodultation distortion in ferroelectric phase shifters depending on bias voltage. Two analog phase shifters based on barium-strontium-titantate (BST) coated sapphire substrates have been fabricated with interdigital capacitors (IDCs) which have 2 and 4 µm spacing between adjacent fingers. In case of the phase shifter with 4 µm-spaced IDCs, a phase shift of more than 121was obtained with a maximum insertion loss of 1.8 dB from 2.4 to 2.5 GHz over a bias voltage range of 0-140 V. The phase shifter with 2 µm-spaced IDCs exhibited a phase shift of more than 135with a maximum insertion loss of 2.37 dB in the same frequency range. In this case, a bias voltage of 80 V was used. Using 2 and 4 µm-spaced phase shifters, a third-order intermodulation (IM3) measurement was carried out with a two-tone cancellation setup to investigate nonlinearity, resulting in an input third-order intercept point (IIP3) of about 30.5 dBm and 38.5 dBm, respectively.

A radio frequency identification tag LSI operating with the carrier frequency of 13.56 MHz as well as storing nonvolatile information in embedded ferroelectric random access memory (FeRAM) has been developed. A full wave rectifier composed of PMOS transistor diodes and NMOS transistor switches achieves RF-to-DC power conversion efficiency over 54%. The entire 16 kbits write and read transaction time can be reduced to 2.1 sec by the use of FeRAM, which corresponds to 2.2 times speed enhancement over conventional EEPROM based tag LSIs. The communication range of the FeRAM based tag LSI can be effectively improved by storing antitheft information in a ferroelectric nonvolatile flip-flop, which can reduce the power consumption of FeRAM from 27 µW to 5 µW. The communication range for the antitheft gate system becomes 70 cm.

Electron emission from PVDF (polyvinylidene-fluoride) ferroelectric substance (thickness: 40 µm) by polarization inversion was realized experimentally with using about 1nm thick C-Au-S semiconductive layer on the surface of a tooth-type electrode. After polarization of the PVDF, a negative impulse voltage (-2400 V with 1-10 ns of wave front and 10-100 ms of wave tail) with a voltage higher than a coercive voltage was applied to the flat-type electrode on the reverse side of the PVDF surface in a vacuum. Then the emitted electrons were detected with using a probe in front of the tooth-type electrode. The detected charge was 6.110-12C.

Circuit techniques to realize stable recall operation and virtually unlimited read/program cycle operations in ferroelectric memory based nonvolatile (NV) SRAM composed of six-transistor and four-ferroelectric capacitor cells have been developed. Unlimited program cycle operation independent of ferroelectric material characteristics is realized by proper control of plate lines. Reliability evaluation results show that the developed memory cell has sufficient operation margin after stresses of temperature, fatigue, DC bias. Application of NV-SRAM to programmable logic devices has been discussed with a prototype of dynamically programmable gate arrays.

A novel ferroelectric-gate transistor with split-gate structure has been proposed and its read out characteristics have been analyzed. "Transistor-type" FeRAMs have a problem in degradation of readout current, i.e. when the readout voltage is applied at the gate, the current of readout operation is smaller than that of write operation. We demonstrate by SPICE simulation that the proposed split-gate structure ferroelectric-FET can overcome the problem.

This paper proposes a new FeRAM design style based on grounded-plate PMOS-gate (GPPG) cell structure. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) VDD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation of a 2.5-V, 2-Mb FeRAM prototype design in a 0.5-µm technology shows a cell array efficiency of 57%, an access time of 85 ns and an active current of 12 mA, respectively.

The design, fabrication, and characterization of monolithic analog phase shifters based on barium-strontium-titanate (BST) coated sapphire substrates with continuously variable 180and 360phase-shift ranges are presented. The phase shifter using a single series resonated termination can provide 180phase shift with the chip area of 4 mm 4 mm. A double series resonated termination in a parallel connection can reach over 370phase shift with better than 6.8 dB-loss at 2.4 GHz. Also, an all-pass network phase shifter composed of only lumped LC elements was described here. This phase shifter demonstrated 160phase shift with an insertion loss of 3.1 dB 1 dB and return loss of better than 10 dB at 2.4 GHz. The total size of the phase shifter is only 2.4 mm 2.6 mm, which is the smallest reported BST phase shifter operating at S-band, to the best of the authors' knowledge.

We developed a novel model for degradation of remanent polarization resulting from repeated polarization reversal cycling. The characteristics of ferroelectric capacitors have been simulated with the double saturation function model that required only five parameters; Ec, Qrmax, Qdmax, Kr and Kd. This novel model combines an equivalent gap capacitor with the double saturation function model. The model predicts hysteresis loops under endurance conditions. The simulated results are well in agreement with the results obtained in the experiment. The model is utilized to quantify the degradation effect of remanent polarization on ferroelectric memory applications.