The paper presents the improvement of out new approach to optimize the process parameter variation, device heat and wire parasitics for analog LSI design by explicitly incorporating various performance estimations into objective functions for placement and routing. To minimize these objective functions, the placement by the simulated annealing method, and maze routing are effectively modified with the perfomance estimation. The improvement results in the excellent performance driven layout for the large size of analog LSIs.

A modern architect can not design high performance computer architecture without thinking all factors of performance from hardware level (logic/layout design) to system level (application programs, operating systems, and compilers). For computer architecture design, there are few practical CAD tools, which support design activities of the architect. In this paper, we propose a CAD tool, called COACH, for computer architecture design. COACH supports architecture design from hardware level to system level. To make a high-performance general purpose computer system, the architect evaluates system performance as well as hardware level performance. To evaluate hardware level performance accurately, logic/layout synthesis tools and simulator are used for evaluation. Logic/layout synthesis tools translate the architecture design into logic circuits and layout pattern and simulator is used to get accurate information on hardware level performance which consists of clock frequency, the number of transistors, power consumption, and so on. To evaluate system level performance, a compiler generator is introducd. The compiler generator generates a compiler of a programming language from the desripition of architecture design. The designed architecture is simulated in the behavior level with programs compiled by the compiler, and the architect can get information on system level performance which consists of program execution steps, etc. From both hardware level performance and system level performance, the architect can evaluate and revise his/her architecture, considering the architecture from hardware level to system level. In this paper, we propose a new design methodology which uses () logic/layout synthesis tools and simulators as tools for architecture design and () a compiler generator for system level evaluation. COACH, a CAD system based on the methodology, is discussed and a prototype of COACH is implemented. Using the design methodology, two processors are designed. The result of the designs shows that the proposed design methodology are effective in architecture design.

The transient scattering of a half sine pulse wave by a conducting rectangular cylinder with an open sidewall is rigorously analyzed by using the point matching method (taking into account the edge condition exactly) combined with the fast inversion of Laplace transform. Numerical results are presented for back scattered and forward scattered responses of the far fields when a half sine pulse is incident on the open side and the closed side of the cylinder. The physical meaning of the transient responses is discussed in detail. The comparison of the responses with those by a perfect conducting rectangular cylinder is presented.

A fully focused Synthetic Aperture Radar (SAR) image can be obtained only if the raw data processing procedure takes into account the space-variance of the SAR system transfer function. This paper presents a nonconventional Fast Fourier Transform (FFT) algorithm which allows an efficient compensation of the space-variant effect. It is specially designed for the SAR data of the Japanese Earth Resources Satellite (JERS-1) but can be extended to different cases.

A new arithmetic multiple-valued algebra with functional completeness is introduced. The algebra is called Neuro-Algebra for it has very similar formula and architecture to neural networks. Two canonical forms of multiple-valued functions of this Neuro-Algebra are presented. Since the arithmetic operations of the Neuro-Aglebra are basically a weighted-sum and a piecewise linear operations, their implementations are very simple and straightforward. Furthermore, the multiple-valued networks based on the Neuro-Algebra can be trained by the traditional back-propagation learning algorithm directly.

We introduce automatic procedures for generating and verifying sufficient correctness properties of synchronous processors. The targeted circuits are synchronous array processors designed from localized, highly regular data dependency graphs (DDGs). The specification, in the form of a DDG, is viewed as a maximally parallel circuit. The implementation, on the other hand, is a (partially) serialized circuit. Since these circuits are not equivalent from an automata-theoretic viewpoint, we define the correctness of the implementation against the specification to mean that a certain relation (called the β-relation) holds between the two. We use a compositional approach to decouple the verification of the control circuitry from that of the data path, thereby gaining efficiency. An array processor in isolation may not have a definite flow of control, because control may reside in the data stream. Therefore, for the purpose of verification, we construct an auxiliary machine, which keeps a timing reference and generates control signals abstracted from a typical data stream. Sufficient correctness conditions are expressed as past-tense computation tree logic (CTL) formulae and verified by CTL model-checking procedures. Experimental results of the verification of a matrix multiplication array and a Gaussian elimination array are presented.

Acceleration techniques have been incorporated into the generalized method of characteristics (GMC) to perform transient analysis of uniform transmission lines, for the special case when the transmission lines are driven by digital signals. These techinques have been proved to improve the simulation speed to a great extent when the analysis is carried out using iterative waveform relaxation method. It has been identified that the load impedance connected to the transmission line has a bearing on the efficiency of one of these acceleration techniques. Examples of an RLCG line terminated with linear loads as well as nonlinear loads are given to illustrate the advantage of incorporating these acceleration techniques.

A complete analysis for the quantization noises and the reconstruction noises of the wavelet pyramid coding system is given. It is shown that in the (orthonormal) wavelet image coding system, there exists a simple and exact formula to compute the reconstruction mean-square-error (MSE) for any kind of quantization errors. Based on the noise analysis, an optimal bit allocation scheme which minimizes the system reconstruction distortion at a given rate is developed. The reconstruction distortion of a wavelet pyramid system is proved to be directly proportional to 2-2, where is a given bit rate. It is shown that, when the optimal bit allocation scheme is adopted, the reconstruction noises can be approximated to white noises. Particularly, it is shown that with only one known quantization MSE of a wavelet decomposition at any layer of the wavelet pyramid, all of the reconstruction MSE's and the quantization MSE's of the coding system can be easily calculated. When uniform quantizers are used, it is shown that at two successive layers of the wavelet pyramid, the optimal quantization step size is a half of its predecessor, which coincides with the resolution version of the wavelet pyramid decomposition. A comparison between wavelet-based image coding and some well-known traditional image coding methods is made by simulations, and the reasons why the wavelet-based image coding is superior to the traditional image coding are explained.

A quantum interconnection scheme by controlling the Coulomb interaction between ballistic electrons is proposed in which 2DEG (2 dimensional electron gas) plays the role of an interconnection medium. This concept brings up new possibilities for the interconnection approach in various fields such as parallel processing, telecommunications switching, and quantum functional devices. Cross-over interconnection, address collision, and address selection in a quantum information network system were analyzed as the first step. The obtained results have shown that the interconnection probability can be controlled by the velocity and timing of the ballistic electron emission from the emitter electrode. The proposed interconnection scheme is expected to open up a new field of quantum effect integrated circuits in the 21st century.

Redundancy is introduced by sampling a bandlimited signal at a higher rate than the Nyquist rate. In the cases of erasures due to fading or jamming, the samples are discarded. Therefore, what we get at the output of the receiver is a set if nonuniform samples obtained from a uniform sampling process with missing samples. As long as the rate of nonuniform samples is higher than the Nyquist rate, the original signal can be recovered with no errors. The sampling theorem can be shown to be equivalent to the fundamental theorem of information theory. This oversampling technique is also equivalent to a convolutional code of infinite constraint length is the Field of real numbers. A DSP implementation of this technique is through the use of a Discrete Fourier Transform (DFT), which happens to be equivalent to block codes in the field of real numbers. An iterative decoder has been proposed for erasure and impulsive noise, which also works with moderate amount of additive random noise. The iterative method is very simple and efficient consisting of modules of Fast Fourier Transforms (FFT) and Inverse FFT's. We also suggest a non-linear iterative method which converges faster than the successive approximation. This iterative decoder can be implemented in a feedback configuration. Besides FFT, other discrete transforms such as Discrete Cosine Transform, Discrete Sine Transform, Discrete Hartley Transform, and Discrete Wavelet Transform are used. The results are comparable to FFT with the advantage of working in the field of real numbers.

A new method by which images are coded with predictable and controllable subjective picture quality in the minimum cost of bit rate is developed. By using wavelet transform, the original image is decomposed into a set of subimages with different frequency channels and resolutions. By utilizing human contrast sensitivity, each decomposed subimage is treated according to its contribution to the total visual quality and to the bit rate. A relationship between physical errors (mainly quantization errors) incurred in the orthonormal wavelet image coding system and the subjective picture quality quantified as the mean opinion score (MOS) is established. Instred of using the traditional optimum bit allocation scheme which minimizes a distortion cost function under the constraint of a given bit rate, we develop an "optimum visually weighted noise power allocation" (OVNA) scheme which emphasizes the satisfying of a desired subjective picture quality in the minumum cost of bit rate. The proposed method enables us to predict and control the picture quality before the reconstruction and to compress images with desired subjective picture quality in the minimum bit rate.

In multidimensional signal sampling, the orthogonal sampling scheme is the simplest one and is employed in various applications, while a non-orthogonal sampling scheme is its alternative candidate. The latter sampling scheme is used mainly in application where the reduction of the sampling rate is important. In three-dimensional (3-D) signal processing, there are two typical sampling schemes which belong to the non-orthogonal samplings; one is face-centered cubic sampling (FCCS) and the other is body-centered cubic sampling (BCCS). This paper proposes a new design method for 3-D band-limiting FIR filters required for such non-orthogonal sampling schemes. The proposed method employs the McClellan transformation technique. Unlike the usual 3-D McClellan transformation, however, the proposed design method uses 2-D prototype filters and 2-D transformation filters to obtain 3-D FIR filters. First, 3-D general sampling theory is discussed and the two types of typical non-orthogonal sampling schemes, FCCS and BCCS, are explained. Then, the proposed design method of 3-D bandlimiting filters for these sampling schemes is explained and an effective implementation of the designed filters is discussed briefly. Finally, design examples are given and the proposed method is compared with other method to show the effectiveness of our methos.

An algorithm interpolating parallel cross-sections between CT slices is described. Contours of equiscalar or constant-density surfaces on cross-sections are directly obtained as non-intersecting loops from grayscale slice images. This algorithm is based on a general algorithm that the authors have proposed earlier, constructing triangulated orientable closed surfaces from grayscale volumes and is particularly suited for a new technique, called laser stereolithography, which creates real 3D plastic objects using UV laser to scan and harden liquid polymer. The process of laser stereolithography is executed slice by slice, and this technique really requires some interpolation of intermediate cross-sections between slices. For visualizing, surfaces are only expected to be shaded almost continuously. The local defects are invisible and not cared about if the picture resolution is rather poor. On the contrary, topological faults are fatal to construct solid models by laser stereolithography, i.e., every contour line on cross-sections must be closed with no intersection. Not a single break of a contour line is tolerated. We already have many algorithms available for equiscalar surface construction, and it seems that if we cut the surfaces, then contour lines could be obtained. However, few of them are directly applicable to solid modeling. Marching cubes algorithm, for example, does not ensure the consistency of surface topology. Our algorithm guarantee an adequate topology of contour lines.

In this paper, we evaluate the sustained performance of the prototype SHD (Super High Definition) image processing system NOVI- HiPIPE, and discuss the requirements of a real-time SHD image processing system. NOVI- HiPIPE is a parallel DSP system with 128 PEs (Processing Elements), each containing one vector processor, and its peak performance is 15 GFLOPS. The measured performance of this system is at least 100 times higher than that of the Cray-2 (single CPU), but is still insufficient for real-time SHD image coding. When coding SHD moving images at 60 frames per second with the JPEG algorithm, the performance must be at least ten times faster than is now possible with NOVI- HiPIPE. To extract higher performance from a parallel processing system, the system architecture must be suitable for the implemented process. The advantages of NOVI- HiPIPE are its mesh network and high performance pipelined vector processor (VP), one of which is installed on each PE. When most basic SHD image coding techniques are implemented on NOVI- HiPIPE, intercommunication occurs only between directly connected PEs, and its cost is very low. Each VP can efficiently execute vector calculations. which occur frequently in image processing, and they increase the performance of NOVI- HiPIPE by a factor of from 20 to 100. In order to further improve the performance, the speed of memory access and bit operation must be increased. The next generation SHD image processing system must be built around the VP, an independent function block which controls memory access, and another block which executes bit operations. To support the input and output of SHD moving images and the inter-frame coding algorithms, the mesh network should be expanded into a 3D-cube.

An approximate equation of the odd periodic correlation distribution for the family of binary sequences is derived from the exact even periodic correlation distribution. The distribution means the probabilities of correlation values which appear among all the phase-shifted sequences in the family. It is shown that the approximate distribution is almost the same as the computational result of some family such as the Gold sequences with low even periodic correlation magnitudes, or the Kasami sequences, the bent sequences with optimal even periodic correlation properties in the sense of the Welch's lower bound. It is also shown that the odd periodic correlation distribution of the family with optimal periodic correlation properties is not the Gaussian distribution, but that of the family of the Gold sequences with short period seems to be similar to the Gaussian distribution.

We discuss possible new principles of information processing by utilizing microscopic, semi-microscopic and macroscopic phenomena occuring in nature. We first discuss quantum mechanical universal information processing in microscopic world governed by quantum mechanics, and then we discuss superconducting phenomena in a mesoscopic system, especially an information processing system using flux quantum. Finally, we discuss macroscopic self-organizing phenomena in biology and suggest possibility of self-organizing devices.

This paper's main objective is to analyze several procedures which select the model g among a set G of stochastic models to minimize the value of an information criterion in the form of L(g)H[g](zn)+(k(g)/2)c(n), where zn is the n observed data emitted by an information source θ which consists of the model gθ∈G and k(gθ) mutually independent stochastic parameters in the model gθ∈G, H[g](zn) is (-1) (the maximum log likelihood value of the data zn with respect to a model g∈G), and c(n) is a predetermined function (penalty function) of n which controls the amount of penalty for increasing the model size. The result is focused on specific performances when the information criteria are applied to the framework of so-called state decomposition. Especially, upper bounds are derived of the following two performance measures for each penalty function c(n): the error probability of the model selection, and the average Kullback-Leibler information between the true information source and the estimated information source.

It is known that the resolution conversion based on orthogonal transform has a problem that is difference of luminance between the converted image and the original. In this paper, the scale factor of the system employing various orthogonal transforms is generally formulated by considering the DC gain, and the condition of alias free for DC component is indicated. If the condition is satisfied, then the scale factor is determined by only the basis functions.

A novel external clocking magnetic disk recording channel is proposed and examined. Timing not only for data recovery but for recording is given by a bit clock which is synchronized with dedicated clock marks on patterned discrete track media. Jitter of the bit clock is 2.5 ns (rms), which is good enough for data rates up to about 20 Mbit/s. Using an MR/Inductive head and PRML (Partial Response Maximum Likelihood) signal processing, an error rate of 110-6 is obtained at linear density 3146 bit/mm.

In this paper we propose a method of formal verfication of fault-tolerance of sequential machines using regular temporal logic. In this method, fault-tolerant properties are described in the form of input-output sequences in regular temporal logic formulas and they are formally verified by checking if they hold for all possible input-output sequences of the machine. We concretely illustrate the method of its application for formal verification of fail-safeness with an example of a comparator for redundant system. The result of verification shows effectiveness of the proposed method.