The effect of NiP as a seed layer for the [Co/Pd]n multilayer perpendicular recording media was studied. It was found that a thin layer of 2 nm NiP inserted between the FeCoC soft magnetic underlayer and the [Co/Pd]n recording layer improved the magnetic properties such as coercivity, squareness and nucleation field. These improvements may be due to the enhanced grain isolation promoted by the NiP seed layer, as well as the lower surface roughness of the NiP seed layer. Read/write test using Guzik spin stand with a ring-type head showed a D50 value 220 kFCI in the roll-off curve. The magnetic transitions recorded up to 390 kFCI for [Co/Pd]n media with the NiP seed layer can be observed clearly with MFM.

In this paper, we present deterministic parallel algorithms for the convex hull of sorted points and their application to a related problem. The algorithms are proposed for the coarse grained multicomputer (CGM) model. We first propose a cost optimal parallel algorithm for computing the problem with a constant number of communication rounds for n/p p2, where n is the size of an input and p is the number of processors. Next we propose a cost optimal algorithm, which is more complicated, for n/p pε, where 0 < ε < 2. From the above two results, we can compute the convex hull of sorted points with O(n/p) computation time and a constant number of communication rounds for n/p pε, where ε > 0. Finally we show an application of our convex hull algorithms. We solve the convex layers for d lines in O((n log n)/p) computation time with a constant number of communication rounds. The algorithm is also cost optimal for the problem.

Wire delays, instead of gate delays, are moving into dominance in modern VLSI design. Current synchronous processors have the critical path not in the ALU function but in the cache access. Since the cache performance enhancement is limited by the memory access delay which mainly consists of wire delays, a reduction in gate delays may no longer imply any enhancement in processor performance. To solve this problem, this paper presents a novel architecture, called the Cascade ALU. The Cascade ALU allows super-scalar processors with future technologies to move the critical path into the ALU part. Therefore the Cascade ALU can enjoy the expected progress in future device speed. Since the delay of the Cascade ALU varies depending on the executed instructions, an asynchronous system is shown to be suitable for implementing the Cascade ALU. However an asynchronous system may have a large handshake overhead, this paper also presents an asynchronous Fine Grain Pipeline technique that hides the handshake overhead. Finally, this paper presents results of performance and area evaluation for an asynchronous implementation of the cascade ALU. The results show that the cascade ALU architecture has a good performance scalability on the reduction of the ALU latency and imposes little area penalty compared with current synchronous processors.

Post annealing treatment for CoCrPt magnetic thin films were tried in different thermal conditions, by changing the time of annealing procedure. Coercivity (Hc) improvement was achieved in annealed sample compared with those as deposited, in which as high as 5.2 kOe has been attained. To clarify the mechanism of annealing treatment on the magnetic properties, X-ray diffraction (XRD) spectrums of those samples and their magnetic properties were carefully studied. Co and Cr lattice parameters were separately calculated from different crystal lattice plane. It was found that a axis lattice spacing of Co hexagonal structure increases monotonically with increased annealing time. Variation of Co hcp peaks significance may due to Cr or Pt redistribution in the crystal grains and its boundaries. Combined with the grain size analysis of Co-rich area by X-ray diffraction peak broaden width, which was not very consistent with the result obtained from other's TEM and AFM studies, Cr diffusion was suggested to be the governing factor at short annealing time region. Co-rich grain growth should also be applied to explain the variation of magnetic properties in longer post annealing.

An analytical solution of the London equation for the weakly coupled grain model of high Tc superconducting thin films has been obtained in the case of finite thickness by taking full account of anisotropic conductivities. Using the solution, we provide general expressions for the transmission-line parameters of high Tc superconducting transmission lines. Dependences of the inductance and resistance on the grain size, coupling strength and film thickness have been numerically evaluated and discussed.

The complex conductivities of high Tc superconducting YBa2Cu3Ox thin films have been studied using the coplanar waveguide resonator technique. In order to evaluate the magnetic penetration depth precisely, we measured the temperature dependence of the resonant frequency and compared it with the numerical results self-consistently. The observed temperature dependence of the complex conductivities is shown to be able to distinguish the effects of the weaklink from the intrinsic property of the grain of an epitaxial thin film and demonstrate the weakly coupled grain model of YBa2Cu3Ox thin films.

This paper proposes a data-localization scheduling scheme inside a processor-cluster for multigrain parallel processing, which hierarchically exploits parallelism among coarsegrain tasks like loops, medium-grain tasks like loop iterations and near-fine-grain tasks like statements. The proposed scheme assigns near-fine-grain or medium-grain tasks inside coarse-grain tasks onto processors inside a processor-cluster so that maximum parallelism can be exploited and inter-processor data transfer can be minimum after data-localization for coarse-grain tasks across processor-clusters. Performance evaluation on a multiprocessor system OSCAR shows that multigrain parallel processing with the proposed data-localization scheduling can reduce execution time for application programs by 10% compared with multigrain parallel processing without data-localization.

We are working on an algorithm to optimize the logic circuits that can be realized on the super fine-grain parallel processing architecture. As a part of this work, we have developed an inverter reduction algorithm. This algorithm is based on modeling logic circuits as dynamical systems. We implement the algorithm in the PARTHENON system, which is the high level synthesis system developed in NTT's laboratories, and evaluate it using ISCAS85 benchmarks. We also compare the results with both the existing algorithm of PARTHENON and the algorithm of Jain and Bryant.

A new finishing method using an advanced ECM assisted by fine abrasive grains was developed, in order to smooth and finish surfaces of 3-dimensional micro components used in micromachines. With the method, a fine surface of selected micro-area, which is not obtained by micro-EDM nor conventional ECM, was obtained in a few minutes. We also developed an advanced machine which has a performance of making 3-D complicated micro structures with fine surfaces by the combination of micro-EDM and the developed finishing method. The performance is achieved by a sequential process from the micro-EDM to the finishing without handling workpiece. Using the new machine, we obtained a high precision shaft with a mirror-like surface. The result is satisfactory to apply the method to making a cylindrical substrate for a rotor of a micro wobble motor. The machining process combined the micro-EDM and the new finishing will be applied to producing micro components such as mechanical parts, mirrors and molding dies.

In the weakly coupled grain model which has been proposed to explain the residual surface resistance in high-Tc superconducting polycrystalline thin films, the superconducting polycrystalline thin films is described as a network of superconducting grains coupled via Josephson junctions. In order to evaluate this model we have fabricated the coplanar waveguide resonator using c-axis oriented YBa2Cu3Ox Thin Films and measured the residual surface resistance. The experimental results are in good agreement with theoretical prediction.

Communication latency is central to multiprocessor design. This study presents the design principles of the EM-X distributed-memory multiprocessor towards tolerating communication latency. The EM-X overlaps computation with communication for latency tolerance by multithreading. In particular, we present two types of hardware support for remote memory access: (1) priority-based packet scheduling for thread invocation, and (2) direct remote memory access. The priority-based scheduling policy extends a FIFO ordered thread invocation policy to adopt to different computational needs. The direct remote memory access is designed to overlap remote memory operations with thread execution. The 80-processor prototype of EM-X is developed and is operational since December 1995. We execute several programs on the machine and evaluate how the EM-X effectively overlaps computation with communication toward tolerating communication latency for high performance parallel computing.

The ultraclean sputtering process (UC-process) was newly introduced in the fabrication of Co62.5Ni30Cr7.5 and Co85.5Cr10.5Ta4 thin film media to establish a new concept in controlling microstructure. UC-process enables the realization of high coercive force Hc up to 2.7-3 kOe in both CoNiCr and CoCrTa media (15/50 nm magnetic/Cr thicknesses) without the decrement of saturation magnetization. The purification of the atmosphere during sputtering and the removal of the adsorbed oxygen impurity on the substrate surface play important roles in obtaining high Hc by applying the UC-process. This high Hc is mainly due to the realization of large magnetocrystalline anisotropy field of grains Hkgrain and low intergranular exchange coupling. UC-process realizes the adequate separation of grains by segregated grain boundaries even in media with thin Cr thickness of 2.5 nm, and enables grain size reduction without the remarkable increment in intergranular exchange coupling. In these media, the reduction of the grain size is most effective for the improvement of readback signal to media noise ratio S/Nm. In the media with grains sufficiently separated by segregated grain boundaries fabricated by the UC-process, control of grain size reduction and further increase in Hc/Hkgrain value through the decrement in intergranular magnetostatic coupling are required to obtain higher S/Nm value.

We have investigated the Josephson microwave self-radiation and the linewidth from different types of YBa2Cu3Oy(YBCO) grain boundary junctions: natural grain boundary junctions, step-edge junctions and bicrystal junctions. The Josephson self-rediation was directly observed using a total power radiometer receiver with receiving frequencies fREC=1.7-72 GHz. All junctions exhibited microwave self-radiation peaks with intensity of order of 10-12-10-14 W. For step-edge and bicrystal junction, they appeared at a voltage related to the Josephson frequency-voltage relation, V=n(h/2e)f, while for natural grain boundary junctions, the above relation did not hold, suggesting a Josephson medium property. For all types of junctions the observed Josephson linewidth deviated from the theoretical RSJ values due to the extra noise source in the grain boundary junction. The Josephson linewidth decreased with increasing the receiving frequency for all type of junctions. The reduction of Josephson linewidth at higher frequencies indicates that the critical current fluctuations due to a critical current spread at small bias voltages and a crystalline disorientation at the junction boundary generate an additional noise in grain boundary junctions.

High temperature superconductors are eminently suitable for use in high frequency devices because of their large energy gap. We fabricated weak link Josephson junctions connected in series. The junctions were constructed of EuBa2Cu3O7-x (EBCO) superconducting thin films on bicrystal MgO substrates. We measured their microwave broadband detection (video detection) characteristics. The responsivity (Sr) of the junctions depended on the bias current and their normal state resistance. The array junctions were effective in increasing normal state resistance. We obtained a maximum Sr of 22.6 [V/W].

Thin (Ba0.75Sr0.25)TiO3 (BST) films to be used as dielectric materials in 256 Mbit DRAM capacitors were investigated. These films were deposited by an rf-sputtering method at substrate temperatures of 480 to 750. As substrate temperature increases, the dielectric constant to the films also increases, from 230 to 550. BST films prepared at temperatures higher than 700 show larger current leaks than films prepared at lower temperatures. A dielectric constant of 250, corresponding to a silicon oxide equivalent thickness (teq) of 0.47 nm, and a leak current density about 110-8 A/cm2 were obtained in 30-nm-thick film deposited at 660. Both of these values are sufficient for use in a 256 Mbit DRAM capacitor.

We have fabricated bi-epitaxial grain boundary junctions in YBa2Cu3O7δ (YBCO) thin films by using SrTiO3 (STO) seed layers on MgO(100) substrate. YBCO film growing over the STO seed layer has a different in-plane orientation from YBCO film without the seed layer, so artificial grain boundaries were created at the edge of the seed layer. The fabricated junctions have high Tc (up to 80 K), and constant-voltage current steps are observed in response to 12.1 GHz microwave radiation. Moreover, some of the junctions show characteristic current-voltage curves comprising not only an usual Josephson-like characteristic but also a low critical current due to the flux creep. This suggests that the two characteristic parts are likely to be connected in series at the junction region.

The performance of copper interconnects formed by the low-kinetic-energy ion bombardment process has been investigated. The copper films formed on SiO2 by this technology under a sufficient amount of ion energy deposition exhibit perfect orientation conversion from Cu (111) to Cu (100) upon post-metallization thermal annealing. We have discovered such crystal orientation conversion is always accompanied by a giant-grain growth as large as 100 µm. The copper film resistivity decreases due to the decrease in the grain boundary scattering, when the giant-grain growth occurs in the film. The resistivity of giant-grain copper film at a room temperature is 1.76 µΩcm which is almost equal to the bulk resistivity of copper. Furthermore, a new-accelerated electromigration life-test method has been developed to evaluate copper interconnects having large electromigration resistance within a very short period of test time. The essence of the new method is the acceleration by a large-current-stress of more than 107 A/cm2 and to utilize the self heating of test interconnect for giving temperature stress. In order to avoid uncontrollable thermal runaway and resultant interconnect melting, we adopted a very efficient cooling system that immediately removes Joule heat and keeps the interconnect temperature constant. As a result, copper interconnects formed by the low-kinetic-energy ion bombardment process exhibit three orders of magnitude longer lifetime at 300 K than Al alloy interconnects.

An adder-based arithmetic VLSI processor using the SD number system is proposed for the applications of real-time computation such as intelligent robot system. Especially in the intelligent robot control system, not only high throughput but also small latency is a very important subject to make quick response for the sensor feedback situation, because the next input sample is obtained only after the robot actually moves. It is essential in the VLSI architecture for the intelligent robot system to make the latency as small as possible. The use of parallelism is an effective approach to reduce the latency. To meet the requirement, an architecture of a new multiple-valued arithmetic VLSI processor is developed. In the processor, addition and subtraction are performed by using the single adderbased processing element (PE). More complex basic arithmetic operations such as multiplication and division are performed by the appropriate data communications between the adder-based PEs with preserving their parallelism. In the proposed architecture, fine-grain parallel processing at the adder-based PE level is realized, and all the PEs can be fully utilized for any parallel arithmetic operations according to adder-based data dependency graph. As a result, the processing speed will be greatly increased in comparison with the conventional parallel processors having the different kinds of the arithmetic PEs such as an adder, a multiplier and a divider. To realize the arithmetic VLSI processor using the adder-based PEs, we introduce the signed-digit (SD) number system for the parallel arithmetic operations because the SD arithmetic has the advantage of modularity as well as parallelism. The multiple-valued bidirectional currentmode technology is also used for the implementation of the compact and high-speed adder-based PE, and the reduction of the number of the interconnections. It is demonstrated that these advantges of the multiple-valued technology are fully used for the implementation of the arithmetic VLSI processor. As a result, the latency of the proposed multiple-valued processor is reduced to 25% that of the binary processor integrated in the same chip size.

Modeling and numerical simulation of crystal growth of Si film and heat transport in 3D structure were made for optimization of physical and geometrical parameters used during laser recrystallization. Based on simulations a new concept called micro-absorber was introduced for obtaining defect-free Si films.