A general-purpose multi-Gbps LVDS driver is presented with a new distortion-free level conversion scheme. For high-speed transmission, a dynamic pre-emphasis scheme is also proposed with overdriving current effectively distributed in time. The proposed LVDS driver achieves supply-insensitive duty preservation with a reduction of switching noise by 50-percent.

A large-swing, high-driving, low-power, class-AB buffer amplifier, which consists of a high-gain input stage and a unity-gain class-AB output stage, with low variation of quiescent current is proposed. The low power consumption and low variation of the quiescent output current are achieved by using a weak-driving and a strong-driving pseudo-source followers. The high-driving capability is mainly provided by the strong-driving pseudo-source follower whose output transistors are turned off in the vicinity of the stable state to reduce the power consumption and the variation of output current, while the quiescent state is maintained by the weak-driving pseudo-source follower. The error amplifiers with source-coupled pairs of the same type transistors are merged into a single error amplifier to reduce the area of the buffer and the current consumption. An experimental prototype buffer amplifier implemented in a 0.35-µm CMOS technology demonstrates that the circuit dissipates an average static power consumption of only 388.7 µW with the standard deviation of only 3.4 µW, which is only 0.874% at a power supply of 3.3 V, and exhibits the slew rates of 2.18 V/µs and 2.50 V/µs for the rising and falling edges, respectively, under a 300 Ω /150 pF load. Both of the second and third harmonic distortions (HD2 and HD3) are -69 dB at 20 kHz under the same load.

This letter proposes an output driver which reduces simultaneous switching noise without degradation of rise/fall time. At the start of transition period, the driver optimally uses both VDD and VSS current by switching of on-chip bypass capacitors. The proposed driver achieves 27-percent reduction in peak current with faster transition time.

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage (VOL) to be equal to the reference voltage (VOL.ref) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1 Gb/s. The worst-case variations of VOL.ref and VOL of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of 20 to 90 and a supply voltage range of 2.25 V to 2.75 V, while the worst-case variation of VOL of the conventional output driver was measured to be 24% within the same ranges of temperature and supply voltage.

A new output driver design called modified asymmetrical slew rate (MASR) output driver was proposed to reduce the simultaneous switching noise without sacrificing switching speed, for high speed and heavy loading applications. The driving capability of the output driver was designed to sink/source 64 mA current @ VOL/VOH = 0.4 V/4.6 V, with 66 pF and 50 Ω loading. When four drivers switch simultaneously, the ground bounce was design to be less than 0.8 V. The performances of the conventional, controlled slew rate (CSR), and MASR output drivers were analyzed by computer simulation. These three types of drivers were implemented with a 0.8 µm CMOS process. The measured ground bounce of the conventional driver is 1.22 V, while the ground bounce of the MASR driver is reduced to 0.72 V. The propagation delays of the conventional and MASR drivers are the same. The performance of the MASR driver is better than that of the CSR driver in all aspects.

A fully on-chip current controlled open-drain output driver using a bandgap reference current generator was designed for high bandwidth DRAMs. It reduces the overhead of receiving a digital code from an external source for the compensation of the temperature and supply voltage variations. The correct value of the current control register is updated at the end of every auto refresh cycle. The operation at the data rate up to 0.8 Gb/s was verified by SPICE simulation using a 0.22 µm triple-well CMOS technology.

A current controlled CMOS output driver was designed by using a temperature-insensitive reference current generator. It eliminates the need for overdesign of the driver transistor size to meet the delay specification at high temperature. Comparison with the conventional CMOS output driver with the same transistor size showed that the ground bounce noise was reduced by 2.5 times and the delay time was increased by 1.4 times, at 25 for 50pF load. The temperature variations of the DC pull-up and pull-down currents of the new output driver were 4% within the temperature range from -15 to 125 compared to the variations of 40 and 60% for pull-up and pull-down respectively for the conventional output driver. The temperature insensitivity of the reference current generator was achieved by multiplying two current components. one which is proportional to mobility and the other which is inversely proportional to mobility, by using a CMOS square root circuit. The temperature variation of the DC output current of the reference current generator alone was 0.77% within the entire temperature range from -15 to 125.