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[Keyword] performance model(16hit)

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  • Performance Modeling of Bitcoin Blockchain: Mining Mechanism and Transaction-Confirmation Process Open Access

    Shoji KASAHARA  

     
    INVITED PAPER

      Pubricized:
    2021/06/09
      Vol:
    E104-B No:12
      Page(s):
    1455-1464

    Bitcoin is one of popular cryptocurrencies widely used over the world, and its blockchain technology has attracted considerable attention. In Bitcoin system, it has been reported that transactions are prioritized according to transaction fees, and that transactions with high priorities are likely to be confirmed faster than those with low priorities. In this paper, we consider performance modeling of Bitcoin-blockchain system in order to characterize the transaction-confirmation time. We first introduce the Bitcoin system, focusing on proof-of-work, the consensus mechanism of Bitcoin blockchain. Then, we show some queueing models and its analytical results, discussing the implications and insights obtained from the queueing models.

  • Energy-Performance Modeling of Speculative Checkpointing for Exascale Systems

    Muhammad ALFIAN AMRIZAL  Atsuya UNO  Yukinori SATO  Hiroyuki TAKIZAWA  Hiroaki KOBAYASHI  

     
    PAPER-High performance computing

      Pubricized:
    2017/07/14
      Vol:
    E100-D No:12
      Page(s):
    2749-2760

    Coordinated checkpointing is a widely-used checkpoint/restart protocol for fault-tolerance in large-scale HPC systems. However, this protocol will involve massive amounts of I/O concentration, resulting in considerably high checkpoint overhead and high energy consumption. This paper focuses on speculative checkpointing, a CPR mechanism that allows for temporal distribution of checkpointings to avoid I/O concentration. We propose execution time and energy models for speculative checkpointing, and investigate energy-performance characteristics when speculative checkpointing is adopted in exascale systems. Using these models, we study the benefit of speculative checkpointing over coordinated checkpointing under various realistic scenarios for exascale HPC systems. We show that, compared to coordinated checkpointing, speculative checkpointing can achieve up to a 11% energy reduction at the cost of a relatively-small increase in the execution time. In addition, a significant energy-performance trade-off is expected when the system scale exceeds 1.2 million nodes.

  • Performance Evaluation of Data Transmission in Maritime Delay-Tolerant-Networks

    Shuang QIN  Gang FENG  Wenyi QIN  Yu GE  Jaya Shankar PATHMASUNTHARAM  

     
    PAPER-Network

      Vol:
    E96-B No:6
      Page(s):
    1435-1443

    In maritime networks, the communication links are characterized as high dynamics due to ship mobility and fluctuation of the sea surface. The performance of traditional transmission protocols is poor in maritime networks. Thus, some researchers have considered using Delay Tolerant Network (DTN) to improve the performance of data transmission in maritime environment. Most existing work on maritime DTNs uses simulation to evaluate the transmission performance in maritime DTNs. In this paper, we develop a theoretical model to analyze the performance of data transmission in maritime DTNs. We first construct a model to describe the ship encounter probability. Then, we use this model to analyze the data delivery ratio from ships in the seaway to the base station (BS) on the coast. Based on the data of tracing the ships navigating in a realistic seaway, we develop a simulator and validate the theoretical models. In addition, by comparing the performance of DTN transmission protocol and traditional end-to-end transmission protocol, we confirm that DTN protocol can effectively improve the performance of data transmission in maritime networks.

  • Joint Tracking of Performance Model Parameters and System Behavior Using a Multiple-Model Kalman Filter

    Zhen ZHANG  Shanping LI  Junzan ZHOU  

     
    PAPER-Software Engineering

      Vol:
    E96-D No:6
      Page(s):
    1309-1322

    Online resource management of a software system can take advantage of a performance model to predict the effect of proposed changes. However, the prediction accuracy may degrade if the performance model does not adapt to the changes in the system. This work considers the problem of using Kalman filters to track changes in both performance model parameters and system behavior. We propose a method based on the multiple-model Kalman filter. The method runs a set of Kalman filters, each of which models different system behavior, and adaptively fuses the output of those filters for overall estimates. We conducted case studies to demonstrate how to use the method to track changes in various system behaviors: performance modeling, process modeling, and measurement noise. The experiments show that the method can detect changes in system behavior promptly and significantly improve the tracking and prediction accuracy over the single-model Kalman filter. The influence of model design parameters and mode-model mismatch is evaluated. The results support the usefulness of the multiple-model Kalman filter for tracking performance model parameters in systems with time-varying behavior.

  • Link Performance Modeling of Interference Rejection Combining Receiver in System Level Evaluation for LTE-Advanced Downlink

    Yousuke SANO  Yusuke OHWATARI  Nobuhiko MIKI  Akihito MORIMOTO  Yukihiko OKUMURA  

     
    PAPER

      Vol:
    E95-B No:12
      Page(s):
    3739-3751

    The interference rejection combining (IRC) receiver, which can suppress inter-cell interference, is effective in improving the cell-edge user throughput. The IRC receiver is typically based on the minimum mean square error (MMSE) criteria, and requires a covariance matrix including the interference signals, in addition to a channel matrix from the serving cell. Therefore, in order to clarify the gain from the IRC receiver, the actual estimation error of these matrices should be taken into account. In a system performance evaluation, the link performance modeling of the IRC receiver, i.e., the output signal-to-interference-plus-noise power ratio (SINR) after IRC reception including the estimation errors, is very important in evaluating the actual performance of the IRC receiver in system level simulations. This is because these errors affect the suppression of the interference signals for the IRC receiver. Therefore, this paper investigates and proposes IRC receiver modeling schemes for the covariance matrix and channel estimation errors. As the modeling scheme for the covariance matrix, we propose a scheme that averages the conventional approximation using the complex Wishart distribution in the frequency domain to address issues that arise in a frequency selective fading channel. Furthermore, we propose a modeling scheme for the channel estimation error according to the ideal channel response of all cells and a channel estimation filter to address channel fading fluctuations. The results of simulations assuming the LTE/LTE-Advanced downlink with two transmitter and receiver antenna branches show that the proposed modeling scheme for the covariance matrix estimation error accurately approximates the performance of a realistic IRC receiver, which estimates the covariance matrix and channel matrix of the serving cell based on the demodulation reference signal (DM-RS), even in a frequency selective fading channel. The results also show that the proposed modeling scheme for the channel estimation error is a robust scheme in terms of the r.m.s. delay spread of a channel model compared to the scheme using the mean square error (MSE) statistic of the estimated channel coefficients based on a channel estimation filter.

  • Modelling Network Performance of End Hosts

    Marat ZHANIKEEV  Yoshiaki TANAKA  

     
    PAPER-Software System

      Vol:
    E95-D No:7
      Page(s):
    1872-1881

    In NGN standards, End Host, also referred to as Terminal Equipment (TE), holds an important place in end-to-end path performance. However, most researchers neglect TE performance when considering performance of end-to-end paths. As far as the authors' knowledge goes, no previous study has proposed a model for TE performance. This paper proposes a method for measuring performance of TE and model extraction based on measurement data. The measurement was made possible with the use of a special NPU (Network Processing Unit) implemented as a programmable NIC. Along with the probing itself, a framework for removing the skew between the NPU and OS is developed in this paper. The multidimensional analysis includes method of probing, packet size and background traffic volume, and studies their effect on TE performance. A method for extracting a generic TE model is proposed. The outcome of this research can be used for modelling TE in simulations and in modelling end-to-end performance when considering QoS in NGN.

  • Performance and Power Modeling of On-Chip Bus System for a Complex SoC

    Hyun LEE  Je-Hoon LEE  Kyoung-Rok CHO  

     
    PAPER-Integrated Electronics

      Vol:
    E93-C No:10
      Page(s):
    1525-1535

    This paper presents latency and power modeling of an on-chip bus at the early stage of SoC design. The latency model is to estimate a bus throughput associated with bus configuration and behavioral model before the system-level modeling for a target SoC is established. The power model roughly calculates the power consumption of an on-chip bus including the power consumed by bus wire and bus logics. Thus, the bus architecture is determined by the trade-off between the bus throughput and power estimation obtained from the proposed bus model. We evaluate the target SoCs such as an MPEG player and a portable multimedia player so as to compare the estimated throughput from the proposed bus model to the result performed by a commercial system-level co-simulation framework. As the simulation results, the latency and power consumption of the proposed model shows 14% and 8% differences compared with the result from the validated commercial co-simulation tool.

  • DCLUE: A Distributed Cluster Emulator

    Krishna KANT  Amit SAHOO  Nrupal JANI  

     
    PAPER-Parallel/Distributed Programming Models, Paradigms and Tools

      Vol:
    E89-D No:2
      Page(s):
    433-440

    Given the availability of high-speed Ethernet and HW based protocol offload, clustered systems using a commodity network fabric (e.g., TCP/IP over Ethernet) are expected to become more attractive for a range of e-business and data center applications. In this paper, we describe a comprehensive simulation to study the performance of clustered database systems using such a fabric. The simulation model currently supports both TCP and SCTP as the transport protocol and models an Oracle 9i like clustered DBMS running a TPC-C like workload. The model can be used to study a wide variety of issues regarding the performance of clustered DBMS systems including the impact of enhancements to network layers (transport, IP, MAC), QoS mechanisms or latency improvements, and cluster-wide power control issues.

  • An Extended Model for TCP Loss Recovery Latency with Random Packet Losses

    Beomjoon KIM  Yong-Hoon CHOI  Jaiyong LEE  

     
    PAPER-Network

      Vol:
    E89-B No:1
      Page(s):
    28-37

    It has been a very important issue to evaluate the performance of transmission control protocol (TCP), and the importance is still growing up because TCP will be deployed more widely in future wireless as well as wireline networks. It is also the reason why there have been a lot of efforts to analyze TCP performance more accurately. Most of these works are focusing on overall TCP end-to-end throughput that is defined as the number of bytes transmitted for a given time period. Even though each TCP's fast recovery strategy should be considered in computation of the exact time period, it has not been considered sufficiently in the existing models. That is, for more detailed performance analysis of a TCP implementation, the fast recovery latency during which lost packets are retransmitted should be considered with its relevant strategy. In this paper, we extend the existing models in order to capture TCP's loss recovery behaviors in detail. On the basis of the model, the loss recovery latency of three TCP implementations can be derived with considering the number of retransmitted packets. In particular, the proposed model differentiates the loss recovery performance of TCP using selective acknowledgement (SACK) option from TCP NewReno. We also verify that the proposed model reflects the precise latency of each TCP's loss recovery by simulations.

  • Trace-Driven Performance Simulation Modeling for Fast Evaluation of Multimedia Processor by Simulation Reuse

    Ho Young KIM  Tag Gon KIM  

     
    PAPER-Simulation and Verification

      Vol:
    E88-A No:12
      Page(s):
    3306-3314

    A method for fast but yet accurate performance evaluation of processor architecture is mostly desirable in modern processors design. This paper proposes one such method which can measure cycle counts and power consumption of pipelined processors. The method first develops a trace-driven performance simulation model and then employs simulation reuse in simulation of the model. The trace-driven performance modeling is for accuracy in which performance simulation uses the same execution traces as constructed in simulation for functional verification. Fast performance simulation can be achieved in a way that performance for each instruction in the traces is evaluated without evaluation of the instruction itself. Simulation reuse supports simulation speedup by elimination of an evaluation at the current state, which is identical to that at a previous state. The reuse approach is based on the property that application programs, especially multimedia applications, have many iterative loops in general. A performance simulator for pipeline architecture based on the proposed method has been developed through which greater speedup has been made compared with other approaches in performance evaluation.

  • Empirical Study on the Improvement of the Usability of a Touch Panel for the Elderly--Comparison of Usability between a Touch Panel and a Mouse--

    Hirokazu IWASE  Atsuo MURATA  

     
    LETTER-Software Engineering

      Vol:
    E86-D No:6
      Page(s):
    1134-1138

    In this study, we clarified the differences in the pointing time required when using a touch panel and a PC mouse for three age groups: young, middle-aged, and elderly. We constructed a performance model for a touch panel operation (Experiment 1). Moreover, we investigated the visual interference caused by a multi-target presentation (Experiment 2). The delay caused by visual interference for the right-hand target was longer than that for the left-hand target, and that for the upper target was longer than that for the lower target.

  • Design Proposals to Assist Older Adults in Using a Computer Mouse

    Hirokazu IWASE  Atsuo MURATA  

     
    LETTER-Welfare Engineering

      Vol:
    E86-D No:1
      Page(s):
    141-145

    In this study, we developed a new performance model that uses an index of difficulty to predict the pointing time required for a pointing task when using a PC mouse. Forty-nine subjects were classified into three age groups: young, middle-aged, and elderly. Experimental factors were the target size, the target distance, and the approach angle to the target. The time for pointing and the coordination of the pointer (mouse cursor) were measured in all conditions. The pointing time was significantly longer for the elderly group than for the young and middle-aged groups. Moreover, the pointing time in each age group tended to increase linearly with an increase in target distance and to decrease as a logarithmic function with an increase in target size. Based on these results, we proposed a new model for measuring performance when operating a PC mouse. Our model received a higher rating for ease-of-use than conventional models. It was clarified that the performance model for elderly persons was different from that for other age groups using the proposed model.

  • State Dependent Multicast Routing for Single Rate Loss Networks

    Chi-Chung CHEUNG  Danny H. K. TSANG  Sanjay GUPTA  

     
    PAPER-Network

      Vol:
    E84-B No:5
      Page(s):
    1388-1396

    We investigate a state dependent multicast routing scheme, called Least Load Multicast Routing (LLMR), for single rate loss networks. The algorithm is based on Least Load Routing (LLR) concept and the approach is to select the least loaded links for establishing connections. An analytical model for LLMR is developed. The accuracy of the analytical model is compared with the simulation results and is found to be very good. We also develop a simplified analytical model for fully symmetrical networks, which is also verified by comparing with simulation results.

  • An Optimistic Cache Consistency Protocol Using Preemptive Approach

    SungHo CHO  Jeong-Hyon HWANG  Kyoung Yul BAE  Chong-Sun HWANG  

     
    PAPER-Databases

      Vol:
    E83-D No:9
      Page(s):
    1772-1780

    In Optimistic Two-Phase Locking (O2PL), when a transaction requests a commit, the transaction can not be committed until all requested locks are obtained. By this reason, O2PL leads to unnecessary waits and operations even though it adopts an optimistic approach. This paper suggests an efficient optimistic cache consistency protocol that provides serializability of committed transactions. Our cache consistency scheme, called PCP (Preemptive Cache Protocol), decides whether to commit or abort without waiting when transactions request commits. In PCP, some transactions that read stale data items can not be aborted, because it adopts a re-ordering scheme to enhance the performance. In addition, for re-ordering, PCP stores only one version of each data item. This paper presents a simulation-based analysis on the performance of PCP with other protocols such as O2PL, Optimistic Concurrency Control and Caching Two-Phase Locking. The simulation experiments show that PCP performs as well as or better than other schemes with low overhead.

  • Non-deterministic Constraint Generation for Analog and Mixed-Signal Layout

    Edoardo CHARBON  Enrico MALAVASI  Paolo MILIOZZI  Alberto SANGIOVANNI-VINCENTELLI  

     
    PAPER-Physical Design

      Vol:
    E80-D No:10
      Page(s):
    1032-1043

    In this paper we propose a comprehensive approach to physical design based on the constraint paradigm. Bounds on the most critical circuit parasitics are automatically generated to help designers and/or physical design tools meet a set of high-level specifications. The constraint generation engine is based on constrained optimization, where various parasitic effects on interconnect and devices are accounted for and dealt with in different manners according to their statistical behavior and their effect on performance.

  • Network IntelligencePerformance by Design

    Roger ACKERLEY  Anne ELVIDGE  Tony INGHAM  John SHEPHERDSON  

     
    INVITED PAPER

      Vol:
    E80-B No:2
      Page(s):
    219-229

    The design and engineering of new network intelligence platforms to accommodate the ever-changing and growing demands of customers, presents rich market opportunities and challenges tempered by concerns arising from the problematic experiences of similar system and network developments. As the telecommunications industry evolves, customers are increasingly coming to expect the perception of instantaneous access to service providers together with transparency to network failures. System performance dictates that response times need to be minimised, sufficient redundant capacity installed in case of failure and controls embedded within the design to manage the exceptional situations (such as media stimulated events) that continually threaten network integrity. Network design based on a 'top-down,' 'end-to-end' methodology plays a fundamental role in delivering solutions that meet customers' performance needs. It is necessary to consider service scenario mixes, service demand, physical network topology, signalling message flows, the mapping of functional entities to physical components, and routing as part of the network design process to ensure that performance requirements are met. The use of 'what-if' design tools is particularly relevant as part of this process. A challenging task faces the System Designer with the often conflicting goals of good performance and provision of service flexibility.