This paper investigates an adaptive notch digital filter that employs normal state-space realization of a single-frequency second-order IIR notch digital filter. An adaptive algorithm is developed to minimize the mean-squared output error of the filter iteratively. This algorithm is based on a simplified form of the gradient-decent method. Stability and frequency estimation bias are analyzed for the adaptive iterative algorithm. Finally, a numerical example is presented to demonstrate the validity and effectiveness of the proposed adaptive notch digital filter and the frequency-estimation bias analyzed for the adaptive iterative algorithm.

The choreography realization problem is a design challenge for systems based on service-oriented architecture. In our previous studies, we studied the problem on a case where choreography was given by one or two scenarios and was expressed by an acyclic relation of events; we introduced the notion of re-constructibility as a property of acyclic relations to be satisfied. However, when choreography is defined by multiple scenarios, the resulting behavior cannot be expressed by an acyclic relation. An event structure is composed of an acyclic relation and a conflict relation. Because event structures are a generalization of acyclic relations, a wider class of systems can be expressed by event structures. In this paper, we propose the use of event structures to express choreography, introduce the re-constructibility of event structures, and show a necessary condition for an event structure to be re-constructible.

Based on the concept of polynomial operators, this paper explores generalized direct-form II structure and its state-space realization for two-dimensional separable-denominator digital filters of order (m, n) where a structure with 3(m+n)+mn+1 fixed parameters plus m+n free parameters is introduced and analyzed. An l2-scaling method utilizing different coupling coefficients at different branch nodes to avoid overflow is presented. Expressions of evaluating the roundoff noise for the filter structure as well as its state-space realization are derived and investigated. The availability of the m+n free parameters is shown to be beneficial as the roundoff noise measures can be minimized with respect to these free parameters by means of an exhaustive search over a set with finite number of candidate elements. The important role these parameters can play in the endeavors of roundoff noise reduction is demonstrated by numerical experiments.

For a service-oriented architecture-based system, the problem of synthesizing a concrete model (i.e., behavioral model) for each peer configuring the system from an abstract specification-which is referred to as choreography-is known as the choreography realization problem. A flow of interaction of peers is called a scenario. In our previous study, we showed conditions and an algorithm to synthesize concrete models when choreography is given by one scenario. In this paper, we extend the study for choreography given by two scenarios. We show necessary and sufficient conditions on the realizability of choreography under both cases where there exist conflicts between scenarios and no conflicts exist.

Block-state realization of state-space digital filters offers reduced implementation complexity relative to canonical state-space filters while filter's internal structure remains accessible. In this paper, we present a quantitative analysis on l2 coefficient sensitivity of block-state digital filters. Based on this, we develop two techniques for minimizing average l2-sensitivity subject to l2-scaling constraints. One of the techniques is based on a Lagrange function and some matrix-theoretic techniques. The other solution method converts the problem at hand into an unconstrained optimization problem which is solved by using an efficient quasi-Newton algorithm where the key gradient evaluation is done in closed-form formulas for fast and accurate execution of quasi-Newton iterations. A case study is presented to demonstrate the validity and effectiveness of the proposed techniques.

For a service-oriented architecture based system, the problem of synthesizing a concrete model, i.e., behavioral model, for each service configuring the system from an abstract specification, which is referred to as choreography, is known as the choreography realization problem. In this paper, we assume that choreography is given by an acyclic relation. We have already shown that the condition for the behavioral model is given by lower and upper bounds of acyclic relations. Thus, the degree of freedom for behavioral models increases; developing algorithms of synthesizing an intelligible model for users becomes possible. In this paper, we introduce several metrics for intelligibility of state machines, and study the algorithm of synthesizing Pareto efficient state machines.

For a service-oriented architecture-based system, the problem of synthesizing a concrete model (i.e., a behavioral model) for each peer configuring the system from an abstract specification — which is referred to as choreography — is known as the choreography realization problem. In this paper, we consider the condition for the behavioral model when choreography is given by an acyclic relation. A new notion called re-constructible decomposition of acyclic relations is introduced, and a necessary and sufficient condition for a decomposed relation to be re-constructible is shown. The condition provides lower and upper bounds of the acyclic relation for the behavioral model. Thus, the degree of freedom for behavioral models increases; developing algorithms for synthesizing an intelligible model for users becomes possible. It is also expected that the condition is applied to the case where choreography is given by a set of acyclic relations.

This paper addresses a noise matching problem for MIMO receiver with mutual coupling in the presence of signal and antenna noise coupling. The matching network in this paper is designed to maximize the system's ergodic capacity by means of minimizing the noise figure matrix. For reducing RF circuit complexity, low noise matching design without crossover elements of the matching circuit is derived for compact symmetrical 2$ imes$2 MIMO receiver system with mutually coupled antenna. Numerical simulation verifies our analytical results and demonstrates the superiority of the proposed matching method among feasible ones. The paper furthermore investigates the lossy matching circuit with the corresponding circuit parameters in a specific condition and the effect of practical matching circuit.

For two-dimensional IIR digital filters described by the Fornasini-Marchesini second model, the problem of jointly optimizing high-order error feedback and realization to minimize the effects of roundoff noise at the filter output subject to l2-scaling constraints is investigated. The problem at hand is converted into an unconstrained optimization problem by using linear-algebraic techniques. The unconstrained optimization problem is then solved iteratively by applying an efficient quasi-Newton algorithm with closed-form formulas for key gradient evaluation. Finally, a numerical example is presented to illustrate the validity and effectiveness of the proposed technique.

A service-oriented architecture builds the entire system using a combination of independent software components. Such an architecture can be applied to a wide variety of computer systems. The problem of synthesizing service implementation models from choreography representing the overall specifications of service interaction is known as the choreography realization problem. In automatic synthesis, software models should be simple enough to be easily understood by software engineers. In this paper, we discuss a semi-formal method for synthesizing hierarchical state machine models for the choreography realization problem. The proposed method is evaluated using metrics for intelligibility.

This paper derives the balanced realizations of second-order analog filters directly from the transfer function. Second-order analog filters are categorized into the following three cases: complex conjugate poles, distinct real poles, and multiple real poles. For each case, simple formulas are derived for the synthesis of the balanced realizations of second-order analog filters. As a result, we obtain closed form expressions of the balanced realizations of second-order analog filters.

In this paper, we present a novel analysis approach for large on-chip power grid circuit analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model order reduction techniques to reduce the circuit matrices before the simulation. Different from the (improved) extended Krylov subspace methods EKS/IEKS, ETBR performs fast truncated balanced realization on response Gramian to reduce the original system. ETBR also avoids the adverse explicit moment representation of the input signals. Instead, it uses spectrum representation in frequency domain for input signals by fast Fourier transformation. The proposed method is very amenable for threading-based parallel computing, as the response Gramian is computed in a Monte-Carlo-like sampling style and each sampling can be computed in parallel. This contrasts with all the Krylov subspace based methods like the EKS method, where moments have to be computed in a sequential order. ETBR is also more flexible for different types of input sources and can better capture the high frequency contents than EKS, and this leads to more accurate results especially for fast changing input signals. Experimental results on a number of large networks (up to one million nodes) show that, given the same order of the reduced model, ETBR is indeed more accurate than the EKS method especially for input sources rich in high-frequency components. If parallel computing is explored, ETBR can be an order of magnitude faster than the EKS/IEKS method.

As we scale toward nanometer technologies, the increase in interconnect parameter variations will bring significant performance variability. New design methodologies will emerge to facilitate construction of reliable systems from unreliable nanometer scale components. Such methodologies require new performance models which accurately capture the manufacturing realities. In this paper, we present a Linear Fractional Transform (LFT) based model for interconnect parametric uncertainty. The new model formulates the interconnect parametric uncertainty as a repeated scalar uncertainty structure. With the help of generalized Balanced Truncation Realization (BTR) and Linear Matrix Inequalities (LMI's), the porposed model reduces the order of the original interconnect network while preserves the stability. The LFT based new model even guarantees passivity if the BTR reduction is based on solutions to a pair of Linear Matrix Inequalities (LMI's) generated from Lur'e equations. In case of large number of uncertain parameters, the new model may be applied successively: the uncertain parameters are partitioned into groups, and with regard to each group, LFT based model is applied in turns.

The passive and sparse reduced-order modeling of a RLC network is presented, where eigenvalues and eigenvectors of the original network are used, and thus the obtained macromodel is more accurate than that provided by the Krylov subspace methods or TBR procedures for a class of circuits. Furthermore, the proposed method is applied to low pass filtering of a reduced-order model produced by these methods without breaking the passivity condition. Therefore, the proposed eigenspace method is not only a reduced-order macromodeling method, but also is embedded in other methods enhancing their performances.

In this paper, we propose a low complexity realization method for compensating for nonlinear distortion. Generally, nonlinear distortion is compensated for by a linearization system using a Volterra kernel. However, this method has a problem of requiring a huge computational complexity for the convolution needed between an input signal and the 2nd-order Volterra kernel. The Simplified Volterra Filter (SVF), which removes the lines along the main diagonal of the 2nd-order Volterra kernel, has been previously proposed as a way to reduce the computational complexity while maintaining the compensation performance for the nonlinear distortion. However, this method cannot greatly reduce the computational complexity. Hence, we propose a subband linearization system which consists of a subband parallel cascade realization method for the 2nd-order Volterra kernel and subband linear inverse filter. Experimental results show that this proposed linearization system can produce the same compensation ability as the conventional method while reducing the computational complexity.

This paper proposes a design method of variable IIR digital filters based on balanced realizations and minimum round-off noise realizations of digital filters. Highly accurate variable digital filters are easily derived by the proposed method. The coefficient matrices of both realizations of second-order digital filters are obtained directly from prototype realizations. The filter coefficients of variable digital filters can be obtained by frequency transformations to the realizations. The filter coefficients are presented as truncated Taylor series for the purpose of reducing a number of calculations to tune the coefficients. However the proposed filters have highly accurate variable characteristics against the coefficient truncation since balanced realizations and minimum round-off noise realizations have very low coefficient sensitivities, which are invariant under the frequency transformations. Moreover, the dynamic ranges of the proposed filters are almost constant against the frequency transformations. Numerical examples show the effectiveness of the variable digital filters designed by the proposed method.

In this paper, we propose a high-speed multiplier-free realization using ROM's to store the results of coefficient scalings in combination with higher signal rate and pipelined operations, without the need of hardware multipliers. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or throughput). Examples are given comparing the proposed realization with the distributed arithmetic (DA) realization and direct-form realization with power-of-two coefficients. Results show that with proper choices of the parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization, while it is much faster than the direct-form with slightly more hardware.

In quantum communication theory, a realization of the optimum quantum receiver that minimizes the error probability is one of fundamental problems. A quantum receiver is described by detection operators. Therefore, it is very important to derive the optimum detection operators for a realization of the optimum quantum receiver. In general, it is difficult to derive the optimum detection operators, except for some simple cases. In addition, even if we could derive the optimum detection operators, it is not trivial what device corresponds to the operators. In this paper, we show a realization method of a quantum receiver which is described by a projection-valued measure (PVM) and apply the method to 3-ary phase-shift-keyed (3PSK) coherent-state signals.

It is an important problem in signal processing, system realization and system identification to find linear discrete-time systems which are consistent with given covariance parameters. This problem is formulated as a problem of finding discrete-time positive real functions which interpolate given covariance parameters. Among various solutions to the problem, a recent remarkable one is a parameterization of all the discrete-time strictly positive real functions that interpolate the covariance parameters and have a limited McMillan degree. In this paper, we use more general input-output characteristics than covariance parameters and consider finding discrete-time positive real functions which interpolate such characteristics. The input-output characteristics are given by the coefficients of the Taylor series at some complex points in the open unit disk. Based on our previous work, we present an algorithm to generate all the discrete-time positive real functions that interpolate the input-output characteristics and have a limited McMillan degree. The algorithm is more general and simpler than the previous one, and is an important practical supplement to the previous work. Moreover, the interpolation of the general input-output characteristics can be effectively applied to the frequency-weighted model reduction. Hence, the algorithm makes a contribution to the problem from the practical viewpoint as well as the theoretical viewpoint.

It is known that AND-EXOR two-level networks obtained by AND-EXOR expressions with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from single-rail-input OR-AND-EXOR expressions and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1 r n). We show that only (r+n/r) tests are required to detect the single stuck-at faults by adding r extra variables to the network.