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[Keyword] reduction(403hit)

61-80hit(403hit)

  • A Weighted Overlapped Block-Based Compressive Sensing in SAR Imaging

    Hanxu YOU  Lianqiang LI  Jie ZHU  

     
    LETTER-Image Processing and Video Processing

      Pubricized:
    2016/12/15
      Vol:
    E100-D No:3
      Page(s):
    590-593

    The compressive sensing (CS) theory has been widely used in synthetic aperture radar (SAR) imaging for its ability to reconstruct image from an extremely small set of measurements than what is generally considered necessary. Because block-based CS approaches in SAR imaging always cause block boundaries between two adjacent blocks, resulting in namely the block artefacts. In this paper, we propose a weighted overlapped block-based compressive sensing (WOBCS) method to reduce the block artefacts and accomplish SAR imaging. It has two main characteristics: 1) the strategy of sensing small and recovering big and 2) adaptive weighting technique among overlapped blocks. This proposed method is implemented by the well-known CS recovery schemes like orthogonal matching pursuit (OMP) and BCS-SPL. Promising results are demonstrated through several experiments.

  • Autoreducibility and Completeness for Partial Multivalued Functions

    Shuji ISOBE  Eisuke KOIZUMI  

     
    PAPER

      Pubricized:
    2016/12/21
      Vol:
    E100-D No:3
      Page(s):
    422-427

    In this paper, we investigate a relationship between many-one-like autoreducibility and completeness for classes of functions computed by polynomial-time nondeterministic Turing transducers. We prove two results. One is that any many-one complete function for these classes is metric many-one autoreducible. The other is that any strict metric many-one complete function for these classes is strict metric many-one autoreducible.

  • An Improved Controller Area Network Data-Reduction Algorithm for In-Vehicle Networks

    Yujing WU  Jin-Gyun CHUNG  

     
    PAPER

      Vol:
    E100-A No:2
      Page(s):
    346-352

    As the number of electronic control units (ECUs) or sensors connected to a controller area network (CAN) bus increases, so does the bus load. When a CAN bus is overloaded by a large number of ECUs, both the waiting time and the error probability of the data transmission are increased. Because the duration of the data transmission is proportional to the frame length, it is desirable to reduce the CAN frame length. In this paper, we present an improved CAN data-reduction (DR) algorithm to reduce the amount of data to be transferred in the CAN frame length. We also implement the data reduction algorithm using the CANoe software, and measure the CAN bus load using a CANcaseXL device. Experimental results with a Kia Sorento vehicle indicate that we can obtain additional average compression ratio of 11.15% with the proposed method compared with the ECANDC algorithm. By using the CANoe software, we show that the average message delay is within 0.10ms and the bus load can be reduced by 23.45% with 20 ECUs using the proposed method compared with the uncompressed message.

  • Detecting Motor Learning-Related fNIRS Activity by Applying Removal of Systemic Interferences

    Isao NAMBU  Takahiro IMAI  Shota SAITO  Takanori SATO  Yasuhiro WADA  

     
    LETTER-Biological Engineering

      Pubricized:
    2016/10/04
      Vol:
    E100-D No:1
      Page(s):
    242-245

    Functional near-infrared spectroscopy (fNIRS) is a noninvasive neuroimaging technique, suitable for measurement during motor learning. However, effects of contamination by systemic artifacts derived from the scalp layer on learning-related fNIRS signals remain unclear. Here we used fNIRS to measure activity of sensorimotor regions while participants performed a visuomotor task. The comparison of results using a general linear model with and without systemic artifact removal shows that systemic artifact removal can improve detection of learning-related activity in sensorimotor regions, suggesting the importance of removal of systemic artifacts on learning-related cerebral activity.

  • Simplified Maximum Likelihood Detection with Unitary Precoding for XOR Physical Layer Network Coding

    Satoshi DENNO  Daisuke UMEHARA  

     
    PAPER-Wireless Communication Technologies

      Pubricized:
    2016/07/19
      Vol:
    E100-B No:1
      Page(s):
    167-176

    This paper proposes novel simplified maximum likelihood detection for XOR physical layer network coding (XOR-PNC) in bi-directional wireless relay systems with Quaternary phase shift keying (QPSK). The proposed detection applies unitary precoding to achieve superior performance without computationally prohibitive exhaustive search. The performance of the XOR employing the proposed simplified MLD with the precoding is analyzed in relay systems with orthogonal frequency division multiplexing (OFDM). The performance of the XOR-PNC with the proposed techniques is also evaluated by computer simulation. The XOR-PNC with the proposed techniques achieves about 7dB better performance than the amplify-and-forward physical layer network coding in the 5-path fading channel at BER=10-4. It is also shown that the XOR-PNC with the proposed techniques achieves better performance than that without precoding.

  • Efficient Balanced Truncation for RC and RLC Networks

    Yuichi TANJI  

     
    PAPER-Circuit Theory

      Vol:
    E100-A No:1
      Page(s):
    266-274

    An efficient balanced truncation for RC and RLC networks is presented in this paper. To accelerate the balanced truncation, sparse structures of original networks are considered. As a result, Lyapunov equations, the solutions of which are necessary for making the transformation matrices, are efficiently solved, and the reduced order models are efficiently obtained. It is proven that reciprocity of original networks is preserved while applying the proposed method. Passivity of the reduced RC networks is also guaranteed. In the illustrative examples, we will show that the proposed method is compatible with PRIMA in efficiency and is more accurate than PRIMA.

  • A New Algorithm for Reducing Components of a Gaussian Mixture Model

    Naoya YOKOYAMA  Daiki AZUMA  Shuji TSUKIYAMA  Masahiro FUKUI  

     
    PAPER

      Vol:
    E99-A No:12
      Page(s):
    2425-2434

    In statistical methods, such as statistical static timing analysis, Gaussian mixture model (GMM) is a useful tool for representing a non-Gaussian distribution and handling correlation easily. In order to repeat various statistical operations such as summation and maximum for GMMs efficiently, the number of components should be restricted around two. In this paper, we propose a method for reducing the number of components of a given GMM to two (2-GMM). Moreover, since the distribution of each component is represented often by a linear combination of some explanatory variables, we propose a method to compute the covariance between each explanatory variable and the obtained 2-GMM, that is, the sensitivity of 2-GMM to each explanatory variable. In order to evaluate the performance of the proposed methods, we show some experimental results. The proposed methods minimize the normalized integral square error of probability density function of 2-GMM by the sacrifice of the accuracy of sensitivities of 2-GMM.

  • A Highly-Adaptable and Small-Sized In-Field Power Analyzer for Low-Power IoT Devices

    Ryosuke KITAYAMA  Takashi TAKENAKA  Masao YANAGISAWA  Nozomu TOGAWA  

     
    PAPER

      Vol:
    E99-A No:12
      Page(s):
    2348-2362

    Power analysis for IoT devices is strongly required to protect attacks from malicious attackers. It is also very important to reduce power consumption itself of IoT devices. In this paper, we propose a highly-adaptable and small-sized in-field power analyzer for low-power IoT devices. The proposed power analyzer has the following advantages: (A) The proposed power analyzer realizes signal-averaging noise reduction with synchronization signal lines and thus it can reduce wide frequency range of noises; (B) The proposed power analyzer partitions a long-term power analysis process into several analysis segments and measures voltages and currents of each analysis segment by using small amount of data memories. By combining these analysis segments, we can obtain long-term analysis results; (C) The proposed power analyzer has two amplifiers that amplify current signals adaptively depending on their magnitude. Hence maximum readable current can be increased with keeping minimum readable current small enough. Since all of (A), (B) and (C) do not require complicated mechanisms nor circuits, the proposed power analyzer is implemented on just a 2.5cm×3.3cm board, which is the smallest size among the other existing power analyzers for IoT devices. We have measured power and energy consumption of the AES encryption process on the IoT device and demonstrated that the proposed power analyzer has only up to 1.17% measurement errors compared to a high-precision oscilloscope.

  • Address Power Reduction Method for High-Resolution Plasma Display Panels Using Address Data Smoothing Based on a Visual Masking Effect

    Masahiko SEKI  Masato FUJII  Tomokazu SHIGA  

     
    PAPER

      Vol:
    E99-C No:11
      Page(s):
    1277-1282

    This paper proposes an address power reduction method for plasma display panels (PDPs) using subfield data smoothing based on a visual masking effect. High-resolution, high-frame-rate PDPs have large address power loss caused by parasitic capacitance. Although the address power is reduced by smoothing the subfield data, noise is generated. The proposed method reduces the address power while maintaining the image quality by choosing the smoothing area of the address data based on the visual masking effect. The results of subjective assessment for the images based on smoothed address data indicate that image quality is maintained.

  • Side-Lobe Reduced, Circularly Polarized Patch Array Antenna for Synthetic Aperture Radar Imaging

    Mohd Zafri BAHARUDDIN  Yuta IZUMI  Josaphat Tetuko Sri SUMANTYO   YOHANDRI  

     
    PAPER

      Vol:
    E99-C No:10
      Page(s):
    1174-1181

    Antenna radiation patterns have side-lobes that add to ambiguity in the form of ghosting and object repetition in SAR images. An L-band 1.27GHz, 2×5 element proximity-coupled corner-truncated patch array antenna synthesized using the Dolph-Chebyshev method to reduce side-lobe levels is proposed. The designed antenna was sim-ulated, optimized, and fabricated for antenna performance parameter measurements. Antenna performance characteristics show good agree-ment with simulated results. A set of antennas were fabricated and then used together with a custom synthetic aperture radar system and SAR imaging performed on a point target in an anechoic chamber. Imaging results are also discussed in this paper showing improvement in image output. The antenna and its connected SAR systems developed in this work are different from most previous work in that this work is utilizing circular polarization as opposed to linear polarization.

  • Lattice Reduction-Aided Detection for Overloaded MIMO Using Slab Decoding

    Ryo HAYAKAWA  Kazunori HAYASHI  Megumi KANEKO  

     
    PAPER-Wireless Communication Technologies

      Vol:
    E99-B No:8
      Page(s):
    1697-1705

    In this paper, we propose an overloaded multiple-input multiple-output (MIMO) signal detection scheme with slab decoding and lattice reduction (LR). The proposed scheme firstly splits the transmitted signal vector into two parts, the post-voting vector composed of the same number of signal elements as that of receive antennas, and the pre-voting vector composed of the remaining elements. Secondly, it reduces the candidates of the pre-voting vector using slab decoding and determines the post-voting vectors for each pre-voting vector candidate by LR-aided minimum mean square error (MMSE)-successive interference cancellation (SIC) detection. From the performance analysis of the proposed scheme, we derive an upper bound of the error probability and show that it can achieve the full diversity order. Simulation results show that the proposed scheme can achieve almost the same performance as the optimal ML detection while reducing the required computational complexity.

  • Efficient Two-Step Middle-Level Part Feature Extraction for Fine-Grained Visual Categorization

    Hideki NAKAYAMA  Tomoya TSUDA  

     
    PAPER-Image Recognition, Computer Vision

      Pubricized:
    2016/02/23
      Vol:
    E99-D No:6
      Page(s):
    1626-1634

    Fine-grained visual categorization (FGVC) has drawn increasing attention as an emerging research field in recent years. In contrast to generic-domain visual recognition, FGVC is characterized by high intra-class and subtle inter-class variations. To distinguish conceptually and visually similar categories, highly discriminative visual features must be extracted. Moreover, FGVC has highly specialized and task-specific nature. It is not always easy to obtain a sufficiently large-scale training dataset. Therefore, the key to success in practical FGVC systems is to efficiently exploit discriminative features from a limited number of training examples. In this paper, we propose an efficient two-step dimensionality compression method to derive compact middle-level part-based features. To do this, we compare both space-first and feature-first convolution schemes and investigate their effectiveness. Our approach is based on simple linear algebra and analytic solutions, and is highly scalable compared with the current one-vs-one or one-vs-all approach, making it possible to quickly train middle-level features from a number of pairwise part regions. We experimentally show the effectiveness of our method using the standard Caltech-Birds and Stanford-Cars datasets.

  • Extended Dual Virtual Paths Algorithm Considering the Timing Requirements of IEC61850 Substation Message Types

    Seokjoon HONG  Ducsun LIM  Inwhee JOE  

     
    PAPER-Information Network

      Pubricized:
    2016/03/07
      Vol:
    E99-D No:6
      Page(s):
    1563-1575

    The high-availability seamless redundancy (HSR) protocol is a representative protocol that fulfills the reliability requirements of the IEC61850-based substation automation system (SAS). However, it has the drawback of creating unnecessary traffic in a network. To solve this problem, a dual virtual path (DVP) algorithm based on HSR was recently presented. Although this algorithm dramatically reduces network traffic, it does not consider the substation timing requirements of messages in an SAS. To reduce unnecessary network traffic in an HSR ring network, we introduced a novel packet transmission (NPT) algorithm in a previous work that considers IEC61850 message types. To further reduce unnecessary network traffic, we propose an extended dual virtual paths (EDVP) algorithm in this paper that considers the timing requirements of IEC61850 message types. We also include sending delay (SD), delay queue (DQ), and traffic flow latency (TFL) features in our proposal. The source node sends data frames without SDs on the primary paths, and it transmits the duplicate data frames with SDs on the secondary paths. Since the EDVP algorithm discards all of the delayed data frames in DQs when there is no link or node failure, unnecessary network traffic can be reduced. We demonstrate the principle of the EDVP algorithm and its performance in terms of network traffic compared to the standard HSR, NPT, and DVP algorithm using the OPNET network simulator. Throughout the simulation results, the EDVP algorithm shows better traffic performance than the other algorithms, while guaranteeing the timing requirements of IEC61850 message types. Most importantly, when the source node transmits heavy data traffic, the EDVP algorithm shows greater than 80% and 40% network traffic reduction compared to the HSR and DVP approaches, respectively.

  • Layer-Aware 3D-IC Partitioning for Area-Overhead Reduction Considering the Power of Interconnections and Pads

    Yung-Hao LAI  Yang-Lang CHANG  Jyh-Perng FANG  Lena CHANG  Hirokazu KOBAYASHI  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E99-A No:6
      Page(s):
    1206-1215

    Through-silicon vias (TSV) allow the stacking of dies into multilayer structures, and solve connection problems between neighboring tiers for three-dimensional (3D) integrated circuit (IC) technology. Several studies have investigated the placement and routing in 3D ICs, but not much has focused on circuit partitioning for 3D stacking. However, with the scaling trend of CMOS technology, the influence of the area of I/O pads, power/ground (P/G) pads, and TSVs should not be neglected in 3D partitioning technology. In this paper, we propose an iterative layer-aware partitioning algorithm called EX-iLap, which takes into account the area of I/O pads, P/G pads, and TSVs for area balancing and minimization of inter-tier interconnections in a 3D structure. Minimizing the quantity of TSVs reduces the total silicon die area, which is the main source of recurring costs during fabrication. Furthermore, estimations of the number of TSVs and the total area are somewhat imprecise if P/G TSVs are not taken into account. Therefore, we calculate the power consumption of each cell and estimate the number of P/G TSVs at each layer. Experimental results show that, after considering the power of interconnections and pads, our algorithm can reduce area-overhead by ~39% and area standard deviation by ~69%, while increasing the quantity of TSVs by only 12%, as compared to the algorithm without considering the power of interconnections and pads.

  • Low PAPR Signal Design for CIOD Using Selected and Clipped QAM Signal

    Ho Kyoung LEE  Changjoong KIM  Seo Weon HEO  

     
    PAPER-Wireless Communication Technologies

      Vol:
    E99-B No:5
      Page(s):
    1143-1150

    Coordinate interleaved orthogonal design (CIOD) using four transmit antennas provides full diversity, full rate (FDFR) properties with low decoding complexity. However, the constellation expansion due to the coordinate interleaving of the rotated constellation results in peak to average power ratio (PAPR) increase. In this paper, we propose two signal constellation design methods which have low PAPR. In the first method we propose a signal constellation by properly selecting the signal points among the expanded square QAM constellation points, based on the co-prime interleaving of the first coordinate signal. We design a regular interleaving pattern so that the coordinate distance product (CPD) after the interleaving becomes large to get the additional coding gain. In the other method we propose a novel constellation with low PAPR based on the clipping of the rotated square QAM constellation. Our proposed signal constellations show much lower PAPR than the ordinary rotated QAM constellations for CIOD.

  • Lattice Reduction Aided Joint Precoding for MIMO-Relay Broadcast Communication

    Yudong MA  Hua JIANG  Sidan DU  

     
    LETTER-Communication Theory and Signals

      Vol:
    E99-A No:4
      Page(s):
    869-873

    In this letter, we propose a lattice reduction (LR) aided joint precoding design for MIMO-relay broadcast communication with the average bit error rate (BER) criterion. We jointly design the signal process flow at both the base station (BS), and the relay station (RS), using the reduced basis of two-stage channel matrices. We further modify the basic precoding design with a novel shift method and a modulo method to improve the power efficiency at the BS and the RS respectively. In addition, the MMSE-SIC algorithm is employed to improve the performance of precoding. Simulations show that, the proposed schemes achieve higher diversity order than the traditional precoding without LR, and the modified schemes significantly outperform the basic design, proving the effectiveness of the proposed methods.

  • A Full-Flexibility-Guaranteed Pin-Count Reduction Design for General-Purpose Digital Microfluidic Biochips

    Trung Anh DINH  Shigeru YAMASHITA  Tsung-Yi HO  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E99-A No:2
      Page(s):
    570-578

    Different from application-specific digital microfluidic biochips, a general-purpose design has several advantages such as dynamic reconfigurability, and fast on-line evaluation for real-time applications. To achieve such superiority, this design typically activates each electrode in the chip using an individual control pin. However, as the design complexity increases substantially, an order-of-magnitude increase in the number of control pins will significantly affect the manufacturing cost. To tackle this problem, several methods adopting a pin-sharing mechanism for general-purpose designs have been proposed. Nevertheless, these approaches sacrifice the flexibility of droplet movement, and result in an increase of bioassay completion time. In this paper, we present a novel pin-count reduction design methodology for general-purpose microfluidic biochips. Distinguished from previous approaches, the proposed methodology not only reduces the number of control pins significantly but also guarantees the full flexibility of droplet movement to ensure the minimal bioassay completion time.

  • A Workload Assignment Policy for Reducing Power Consumption in Software-Defined Data Center Infrastructure

    Takaaki DEGUCHI  Yoshiaki TANIGUCHI  Go HASEGAWA  Yutaka NAKAMURA  Norimichi UKITA  Kazuhiro MATSUDA  Morito MATSUOKA  

     
    PAPER-Energy in Electronics Communications

      Vol:
    E99-B No:2
      Page(s):
    347-355

    In this paper, we propose a workload assignment policy for reducing power consumption by air conditioners in data centers. In the proposed policy, to reduce the air conditioner power consumption by raising the temperature set points of the air conditioners, the temperatures of all server back-planes are equalized by moving workload from the servers with the highest temperatures to the servers with the lowest temperatures. To evaluate the proposed policy, we use a computational fluid dynamics simulator for obtaining airflow and air temperature in data centers, and an air conditioner model based on experimental results from actual data center. Through evaluation, we show that the air conditioners' power consumption is reduced by 10.4% in a conventional data center. In addition, in a tandem data center proposed in our research group, the air conditioners' power consumption is reduced by 53%, and the total power consumption of the whole data center is exhibited to be reduced by 23% by reusing the exhaust heat from the servers.

  • A Tightly-Secure Multisignature Scheme with Improved Verification

    Jong Hwan PARK  Young-Ho PARK  

     
    PAPER-Cryptography and Information Security

      Vol:
    E99-A No:2
      Page(s):
    579-589

    A multisignature (MS) scheme enables a group of signers to produce a compact signature on a common message. In analyzing security of MS schemes, a key registration protocol with proof-of-possession (POP) is considered to prevent rogue key attacks. In this paper, we refine the POP-based security model by formalizing a new strengthened POP model and showing relations between the previous POP models and the new one. We next suggest a MS scheme that achieves: (1) non-interactive signing process, (2) O(1) pairing computations in verification, (3) tight security reduction under the co-CDH assumption, and (4) security under the new strengthened POP model. Compared to the tightly-secure BNN-MS scheme, the verification in ours can be at least 7 times faster at the 80-bit security level and 10 times faster at the 128-bit security level. To achieve our goal, we introduce a novel and simple POP generation method that can be viewed as a one-time signature without random oracles. Our POP technique can also be applied to the LOSSW-MS scheme (without random oracles), giving the security in the strengthened POP model.

  • Sub-Band Noise Reduction in Multi-Channel Digital Hearing Aid

    Qingyun WANG  Ruiyu LIANG  Li JING  Cairong ZOU  Li ZHAO  

     
    LETTER-Speech and Hearing

      Pubricized:
    2015/10/14
      Vol:
    E99-D No:1
      Page(s):
    292-295

    Since digital hearing aids are sensitive to time delay and power consumption, the computational complexity of noise reduction must be reduced as much as possible. Therefore, some complicated algorithms based on the analysis of the time-frequency domain are very difficult to implement in digital hearing aids. This paper presents a new approach that yields an improved noise reduction algorithm with greatly reduce computational complexity for multi-channel digital hearing aids. First, the sub-band sound pressure level (SPL) is calculated in real time. Then, based on the calculated sub-band SPL, the noise in the sub-band is estimated and the possibility of speech is computed. Finally, a posteriori and a priori signal-to-noise ratios are estimated and the gain function is acquired to reduce the noise adaptively. By replacing the FFT and IFFT transforms by the known SPL, the proposed algorithm greatly reduces the computation loads. Experiments on a prototype digital hearing aid show that the time delay is decreased to nearly half that of the traditional adaptive Wiener filtering and spectral subtraction algorithms, but the SNR improvement and PESQ score are rather satisfied. Compared with modulation frequency-based noise reduction algorithm, which is used in many commercial digital hearing aids, the proposed algorithm achieves not only more than 5dB SNR improvement but also less time delay and power consumption.

61-80hit(403hit)