Dimensionality reduction is one of the important preprocessing steps in practical pattern recognition. SEmi-supervised Local Fisher discriminant analysis (SELF)--which is a semi-supervised and local extension of Fisher discriminant analysis--was shown to work excellently in experiments. However, when data dimensionality is very high, a naive use of SELF is prohibitive due to high computational costs and large memory requirement. In this paper, we introduce computational tricks for making SELF applicable to large-scale problems.

How to reduce noise with less speech distortion is a challenging issue for speech enhancement. We propose a novel approach for reducing noise with the cost of less speech distortion. A noise signal can generally be considered to consist of two components, a "white-like" component with a uniform energy distribution and a "color" component with a concentrated energy distribution in some frequency bands. An approach based on noise eigenspace projections is proposed to pack the color component into a subspace, named "noise subspace". This subspace is then removed from the eigenspace to reduce the color component. For the white-like component, a conventional enhancement algorithm is adopted as a complementary processor. We tested our algorithm on a speech enhancement task using speech data from the Texas Instruments and Massachusetts Institute of Technology (TIMIT) dataset and noise data from NOISEX-92. The experimental results show that the proposed algorithm efficiently reduces noise with little speech distortion. Objective and subjective evaluations confirmed that the proposed algorithm outperformed conventional enhancement algorithms.

CMOS circuits consume great dynamic power in switching. It has been proposed that energy transfer through a rising Vdd dissipates small amounts of energy. In typical power gate circuits, the high-performance PMOS transistors (PSW) that connect the circuit blocks to the power supply reduce leakage power by shutting off outer power (Vdd) to the idle blocks. We expand this technique by utilizing active PSW, which are turned on and off by clock signal. The PSW are fully turned on only for half of each clock cycle. This means that sufficient Vdd is provided to the circuit continuously for half of each clock cycle. In this manner, the circuit charge and discharge actions are cycle occur in different phases, and ramp Vdd is supplied to the designed circuit; we name this technique "CKVdd." CKVdd is a clock-controlled self-stabilized voltage technique, which generates stable ramp voltage to suppress the currents effectively. It is proposed to reduce dynamic power dissipation in conventional CMOS digital circuits. As compared to the conventional circuit, the circuits using CKVdd technique possesses several characteristics that differ from those of the current circuits using constant Vdd power source. First, CKVdd technique combines the power source and clock signal; it is an efficient low power technique. Second, CKVdd propose a feasible method to generate ramp-Vdd and low-Vdd. This technique would be convenient used to design generic low power digital circuits. Third, normal CMOS circuits show the dynamic power consumption increase proportional to the clock frequency. CKVdd results in a lower-than-usual frequency dependency, it is suitable used to design high clock speed circuits. In investigating constant Vdd for MPEG VLD decoders, CKVdd-circuit reduces 48% of the usual power dissipation and 88% of the usual peak current with small delay penalty.

In this letter, a pre-processed lattice reduction (PLR) scheme is developed for the lattice reduction aided (LRA) detection of multiple input multiple-output (MIMO) systems in spatially correlated channel. The PLR computes the LLL-reduced matrix of the equivalent matrix, which is the product of the present channel matrix and unimodular transformation matrix for LR of spatial correlation matrix, rather than the present channel matrix itself. In conjunction with PLR followed by recursive lattice reduction (RLR) scheme [7], pre-processed RLR (PRLR) is shown to efficiently carry out the LR of the channel matrix, especially for the burst packet message in spatially and temporally correlated channel while matching the performance of conventional LRA detection.

As we scale toward nanometer technologies, the increase in interconnect parameter variations will bring significant performance variability. New design methodologies will emerge to facilitate construction of reliable systems from unreliable nanometer scale components. Such methodologies require new performance models which accurately capture the manufacturing realities. In this paper, we present a Linear Fractional Transform (LFT) based model for interconnect parametric uncertainty. The new model formulates the interconnect parametric uncertainty as a repeated scalar uncertainty structure. With the help of generalized Balanced Truncation Realization (BTR) and Linear Matrix Inequalities (LMI's), the porposed model reduces the order of the original interconnect network while preserves the stability. The LFT based new model even guarantees passivity if the BTR reduction is based on solutions to a pair of Linear Matrix Inequalities (LMI's) generated from Lur'e equations. In case of large number of uncertain parameters, the new model may be applied successively: the uncertain parameters are partitioned into groups, and with regard to each group, LFT based model is applied in turns.

Nonnegative matrix factorization (NMF) and its extensions such as Nonnegative Tensor Factorization (NTF) have become prominent techniques for blind sources separation (BSS), analysis of image databases, data mining and other information retrieval and clustering applications. In this paper we propose a family of efficient algorithms for NMF/NTF, as well as sparse nonnegative coding and representation, that has many potential applications in computational neuroscience, multi-sensory processing, compressed sensing and multidimensional data analysis. We have developed a class of optimized local algorithms which are referred to as Hierarchical Alternating Least Squares (HALS) algorithms. For these purposes, we have performed sequential constrained minimization on a set of squared Euclidean distances. We then extend this approach to robust cost functions using the alpha and beta divergences and derive flexible update rules. Our algorithms are locally stable and work well for NMF-based blind source separation (BSS) not only for the over-determined case but also for an under-determined (over-complete) case (i.e., for a system which has less sensors than sources) if data are sufficiently sparse. The NMF learning rules are extended and generalized for N-th order nonnegative tensor factorization (NTF). Moreover, these algorithms can be tuned to different noise statistics by adjusting a single parameter. Extensive experimental results confirm the accuracy and computational performance of the developed algorithms, especially, with usage of multi-layer hierarchical NMF approach [3].

This paper analyzes the spurious sources in DDS synthesizers and deduces the simple model of DDS output signal. The method of feeding pseudo-random noise into the phase accumulator for spurious reduction is discussed. A new method for spurious reduction by compensating for DAC integer nonlinearity is proposed with two DACs and a power combiner. One DAC generates the error signal to compensate for the other DAC INL. The factor how the amplitude error and the phase error between the two combined signals affect the spurious level is also analyzed. The experiment shows that the spurious reduction can be improved by at least 18 dB, which proves the validity of the DAC INL compensation method for the spurious reduction.

The wireless systems that establish multiple input multiple output (MIMO) channels through multiple antennas at both ends of the communication link, have been proved to have tremendous potential to linearly lift the capacity of conventional scalar channel. In this paper, we present two efficient decision feedback equalization algorithms that achieve optimal and suboptimal detection order in MIMO spatial multiplexing systems. The new algorithms combine the recursive matrix inversion and ordered QR decomposition approaches, which are developed for nulling cancellation interaface Bell Labs layered space time (BLAST) and back substitution interface BLAST. As a result, new algorithms achieve total reduced complexities in frame based transmission with various payload lengths compared with the earlier methods. In addition, they enable shorter detection delay by carrying out a fast hybrid preprocessing. Moreover, the operation precision insensitivity of order optimization greatly relaxes the word length of matrix inversion, which is the most computational intensive part within the MIMO detection task.

The authors present R2Power, an effective approach to the realizable reduction of RC networks with independent current sources. The proposed approach is based on the entrywise perturbation theory for diagonally dominant M-matrices. The accuracy of the node voltages of the reduced network, as compared to those of the original network, is maintained on the order of the entrywise perturbation performed during reduction. R2Power can be used to reduce the size of RC networks used to model the power networks of SoCs, for efficient IR-drop analysis. Experiments showed that R2Power reduced the size of industrial examples by more than 95%, with maximum relative node voltage errors of less than 0.012%.

When a store sells items to customers, the store wishes to determine the prices of the items to maximize its profit. Intuitively, if the store sells the items with low (resp. high) prices, the customers buy more (resp. less) items, which provides less profit to the store. So it would be hard for the store to decide the prices of items. Assume that the store has a set V of n items and there is a set E of m customers who wish to buy those items, and also assume that each item i ∈ V has the production cost di and each customer ej ∈ E has the valuation vj on the bundle ej ⊆ V of items. When the store sells an item i ∈ V at the price ri, the profit for the item i is pi=ri-di. The goal of the store is to decide the price of each item to maximize its total profit. We refer to this maximization problem as the item pricing problem. In most of the previous works, the item pricing problem was considered under the assumption that pi ≥ 0 for each i ∈ V, however, Balcan, et al. [In Proc. of WINE, LNCS 4858, 2007] introduced the notion of "loss-leader," and showed that the seller can get more total profit in the case that pi < 0 is allowed than in the case that pi < 0 is not allowed. In this paper, we derive approximation preserving reductions among several item pricing problems and show that all of them have algorithms with good approximation ratio.

In multiple antenna systems that use spatial multiplexing to raise transmission rates, it is preferable to use maximum likelihood (ML) detection to exploit the full receive diversity and minimize the error probability. In this paper, we present two tree based approximate ML detectors that use new two ordering criteria in conjunction with efficient search strategies. Unlike conventional tree detectors, the new detectors closely approximate the error performance of the exact ML detector while achieving a dramatic reduction in complexity. Moreover, they ensure a fixed detection delay and high level of parallelization in the tree search.

We have proposed a noise reduction method based on a noise reconstruction system (NRS). The NRS uses a linear prediction error filter (LPEF) and a noise reconstruction filter (NRF) which estimates background noise by system identification. In case a fixed step size for updating tap coefficients of the NRF is used, it is difficult to reduce background noise while maintaining the high quality of enhanced speech. In order to solve the problem, a variable step size is proposed. It makes use of cross-correlation between an input signal and an enhanced speech signal. In a speech section, a variable step size becomes small so as not to estimate speech, on the other hand, large to track the background noise in a non-speech section.

Recently, a data-selective method has been proposed to achieve low misalignment in affine projection algorithm (APA) by keeping the condition number of an input data matrix small. We present an improved method, and a complexity reduction algorithm for the APA with the data-selective method. Experimental results show that the proposed algorithm has lower misalignment and a lower condition number for an input data matrix than both the conventional APA and the APA with the previous data-selective method.

The reduction of the peak power consumption of LSI is required to reduce the instability of gate operation, the delay increase, the noise, and etc. It is possible to reduce the peak power consumption by clock scheduling because it controls the switching timings of registers and combinational logic elements. In this paper, we propose a fast peak power wave estimation method for clock scheduling and fast clock scheduling methods for the peak power reduction. In experiments, it is shown that the peak power wave estimated by the proposed method in a few seconds is highly correlated with the peak power wave obtained by HSPICE simulation in several days. By using the proposed peak power wave estimation method, proposed clock scheduling methods find clock schedules that greatly reduce the peak power consumption in a few minutes.

The share of leakage in cache power consumption increases with technology scaling. Choosing a higher threshold voltage (Vth) and/or gate-oxide thickness (Tox) for cache transistors improves leakage, but impacts cell delay. We show that due to uncorrelated random within-die delay variation, only some (not all) of cells actually violate the cache delay after the above change. We propose to add a spare cache way to replace delay-violating cache-lines separately in each cache-set. By SPICE and gate-level simulations in a commercial 90 nm process, we show that choosing higher Vth, Tox and adding one spare way to a 4-way 16 KB cache reduces leakage power by 42%, which depending on the share of leakage in total cache power, gives up to 22.59% and 41.37% reduction of total energy respectively in L1 instruction- and L2 unified-cache with a negligible delay penalty, but without sacrificing cache capacity or timing-yield.

Leakage power consumption of logic elements has become a serious problem, especially in the sub-100-nanometer process. In this paper, a novel power gating approach by using the controlling value of logic elements is proposed. In the proposed method, sleep signals of the power-gated blocks are extracted completely from the original circuits without any extra logic element. A basic algorithm and a probability-based heuristic algorithm have been developed to implement the basic idea. The steady maximum delay constraint has also been introduced to handle the delay issues. Experiments on the ISCAS'85 benchmarks show that averagely 15-36% of logic elements could be power gated at a time for random input patterns, and 3-31% of elements could be stopped under the steady maximum delay constraints. We also show a power optimization method for AND/OR tree circuits, in which more than 80% of gates can be power-gated.

It is essential to ensure a satisfactory QoS (Quality of Service) when offering a speech communication system with a noise reduction algorithm. In this paper, we propose a new obejective test methodology for noise-reduced speech that estimates word intelligibility by using a distortion measure. Experimental results confirmed that the proposed methodology gives an accurate estimate with independence of noise reduction algorithms and noise types.

In this paper, we propose a method for selecting n-mode singular vectors in higher-order singular value decomposition. We select the minimum number of n-mode singular vectors, when the upper bound of a least-squares cost function is thresholded. The reduced n-ranks of all modes of a given tensor are determined automatically and the tensor is represented with the minimum number of dimensions. We apply the selection method to simultaneous low rank approximation of matrices. Experimental results show the effectiveness of the n-mode singular vector selection method.

Point Pattern Matching (PPM) is an essential problem in many image analysis and computer vision tasks. This paper presents a two-stage algorithm for PPM problem using ellipse fitting and dual Hilbert scans. In the first matching stage, transformation parameters are coarsely estimated by using four node points of ellipses which are fitted by Weighted Least Square Fitting (WLSF). Then, Hilbert scans are used in two aspects of the second matching stage: it is applied to the similarity measure and it is also used for search space reduction. The similarity measure named Hilbert Scanning Distance (HSD) can be computed fast by converting the 2-D coordinates of 2-D points into 1-D space information using Hilbert scan. On the other hand, the N-D search space can be converted to a 1-D search space sequence by N-D Hilbert Scan and an efficient search strategy is proposed on the 1-D search space sequence. In the experiments, we use both simulated point set data and real fingerprint images to evaluate the performance of our algorithm, and our algorithm gives satisfying results both in accuracy and efficiency.

This paper describes the matrix order reduction method by the nodal analysis formulation and the application of relaxation-based simulation technique to interconnect and plane networks. First, the characteristics of the power/ground plane networks are considered. Next, the formulation of the plane network by nodal analysis (NA) method is suggested. Furthermore, application and estimation results of the relaxation-based numerical analyses are shown. Finally, it is confirmed that the relaxation-based methods improved by the suggested formulation are much more efficient than the conventional direct-based methods.