The authors propose a system for searching the shape of human hands and fingers in real time and with high accuracy, without using any special peripheral equipment such as range sensor, PC cluster, etc., by a method of retrieving similar image quickly with high accuracy from a large volume of image database containing the complicated shapes and self-occlusions. In designing the system, we constructed a database in a way to be adaptable even to differences among individuals, and searched CG images of hand similar to unknown hand image, through extraction of characteristics using high-order local autocorrelational patterns, reduction of the amount of characteristics centering on principal component analysis, and prior rearrangement of data corresponding to the amount of characteristics. As a result of experiments, our system performed high-accuracy estimation of human hand shape where mean error was 7 degrees in finger joint angles, with the processing speed of 30 fps or over.

This paper proposes the design to reduce the number of fed elements by replacing with parasitic elements in an array antenna. The study depends on the analysis of electromagnetic wave fields in consideration of the coupling between the half-wavelength dipoles. The case of 2 fed elements and 2 parasitic elements is considered as a unit cell to form the total array. After optimizing the element arrangement, the antenna gain can match that of the equivalent 4-fed element case. Feeding networks in a high power radiating system are analyzed in terms of the length and matching of feed lines, and the arrangement of amplifiers.

Fast and simple algorithm of a parity checker for a large residue numbers is presented. A new set of RNS moduli with 2r-(2l1) form for fast modular multiplication is proposed. The proposed RNS moduli has a large dynamic range for a large RNS number. The parity of a residue number can be checked by the Chinese remainder theorem (CRT). A CRT-based parity checker is simply organized by the Montgomery reduction method (MRM), implemented by using multipliers and the carry-save adder array. We present a fast parity checker with minimal hardware processed in three clock cycles for 32-bit RNS modulus set.

In this paper, we propose a new error feedback (EF) structure for 2-D separable-denominator digital filters described by a rational transfer function. In implementing two-dimensional separable-denominator digital filters, the minimum delay elements structures are common. In the proposed structure, the filter feedback-loop corresponding to denominator polynomial is placed at a different location compared to the commonly used structures. The proposed structure can minimize the roundoff noise more than the previous structure though the number of multipliers is less than that of previous one. Finally, we present a numerical example by designing the EF on the proposed structure and demonstrate the effectiveness of the proposed method.

In this paper, a complete X-tolerant test data compression solution is proposed for system-on-a-chip (SOC) testing. The solution achieves low-cost testing by employing not only selective Huffman vertical coding (SHVC) for test stimulus compression but also MISR-based time compactor for test response compaction. Moreover, the solution is non-intrusive, since it can tolerate any number of unknown states (also called X state) in test responses such that it does not require modifying the logic of core to eliminate or block the sources of unknown states. Furthermore, the solution achieves enhanced diagnosis capability over conventional MISR. The enhanced diagnosis requires the least hardware overhead by reusing the existing masking logic and achieves significant saving in diagnostic time. Experimental results for ISCAS 89 benchmarks as well as the evaluation of hardware implementation have proven the efficiency of the proposed test solution.

The authors realize a 50% length reduction of short-slot couplers in a post-wall dielectric substrate by two techniques. One is to introduce hollow rectangular holes near the side walls of the coupled region. The difference of phase constant between the TE10 and TE20 propagating modes increases and the required length to realize a desired dividing ratio is reduced. Another is to remove two reflection-suppressing posts in the coupled region. The length of the coupled region is determined to cancel the reflections at both ends of the coupled region. The total length of a 4-way Butler matrix can be reduced to 48% in comparison with the conventional one and the couplers still maintain good dividing characteristics; the dividing ratio of the hybrid is less than 0.1 dB and the isolations of the couplers are more than 20 dB.

Recently, automatic speech recognition in a car has practical uses for applications like car-navigation and hands-free telephone dialers. For noise robustness, the current successes are based on the assumption that there is only a stationary cruising noise. Therefore, the recognition rate is greatly reduced when there is music or news coming from a radio or a CD player in the car. Since reference signals are available from such in-vehicle units, there is great hope that echo cancellers can eliminate the echo component in the observed noisy signals. However, previous research reported that the performance of an echo canceller is degraded in very noisy conditions. This implies it is desirable to combine the processes of echo cancellation and noise reduction. In this paper, we propose a system that uses echo cancellation and spectral subtraction simultaneously. A stationary noise component for spectral subtraction is estimated through the adaptation of an echo canceller. In our experiments, this system significantly reduced the errors in automatic speech recognition compared with the conventional combination of echo cancellation and spectral subtraction.

A method is proposed to compute moments of distributed coupled RLC interconnects. Both uniform line models and non-uniform line models will be developed. Considering both self inductances and mutual inductances in multi-conductors, recursive moment computations formulae of lumped coupled RLC interconnects are extended to those of distributed coupled RLC interconnects. By using the moment computation technique in conjunction with the projection-based order reduction method, the inductive crosstalk noise waveform can be accurately and efficiently estimated. Fundamental developments of the proposed approach will be described. Simulation results demonstrate the improved accuracy of the proposed method over the traditional lumped methods.

This paper presents a reduced-complexity maximum likelihood detection (MLD) scheme for orthogonal frequency division multiplexing with space division multiplexing (OFDM-SDM) systems. Original MLD is known to be an optimal scheme for detecting the spatially multiplexed signals. However, MLD suffers from an exponentially computational complexity because it involves an exhaustive search for the optimal result. In this paper, we propose a novel detection scheme, which drastically reduce the complexity of MLD while keeping performance losses small. The proposed scheme decouples the spatially multiplexed signals in two stages. In stage one, the estimated symbols obtained from zero-forcing (ZF) are used to limit the candidate symbol vectors. In stage two, to form a final estimate of the transmitted symbol vector, the Euclidean or original defined likelihood metric is examined over all symbol vectors obtained from stage 1. Both the bit error rate (BER) and packet error rate (PER) performances are evaluated over a temporally and spatially uncorrelated frequency selective channel through the computer simulations. For a four-transmit and four-receive OFDM-SDM system transmitting data at 144 Mbit/s and 216 Mbit/ss i.e., employing 16 Quadrature Amplitude Modulation (16QAM) and 64QAM subcarrier modulation over 16.6 MHz bandwidth channel, the degradation in required SNR from MLD for PER = 1% are about 0.6 dB and 1.5 dB, respectively. However, the complexity of MLD is reduced to 0.51000% and 0.01562%.

This paper presents a deformable fast computation elastic model for real-time processing applications. 'Gradational element resolution model' is introduced with fewer elements for fast computation, in which small elements are laid around the object surface and large elements are laid in the center of the object. Elastic element layout is changed dynamically according to the deformation of cutting or tearing objects. The element reconstruction procedure is applied little by little for each step of the recursive motion generation process to avoid an increase in motion computation time.

In the Reconfigurable System-On-a-Chip (RSOC), an FPGA core is embedded to improve the design flexibility of SOC. In this paper, we demonstrate that the embedded FPGA core is also feasible for use in implementing the proposed hybrid pattern Built-In Self-Test (BIST) in order to reduce the test cost of SOC. The hybrid pattern BIST, which combines Linear Feedback Shift Register (LFSR) with the proposed on-chip Deterministic Test Pattern Generator (DTPG), can achieve not only complete Fault Coverage (FC) but also minimum test sequence by applying a selective number of pseudorandom patterns. Furthermore, the hybrid pattern BIST is designed under the resource constraint of target FPGA core so that it can be implemented on any size of FPGA core and take full advantage of the target FPGA resource to reduce test cost. Moreover, the reconfigurable core-based approach has minimum hardware overhead since the FPGA core can be reconfigured as normal mission logic after testing such that it eliminates the hardware overhead of BIST logic. Experimental results for ISCAS 89 benchmarks and a platform FPGA chip have proven the efficiency of the proposed approach.

A new hybrid method for characterizing the irregular power/ground plane pair is developed in this paper by combining the conventional eigen-mode expansion method with the new-presented inverted composition method and a simple model order reduction. By the approach, the eigen-mode expansion method can be extended to the characteristics research of the power/ground plane pair with holes. In this gridless method, ports and decoupling capacitors can be arbitrarily placed on the plane pair. The numerical example demonstrates its good validity.

In this letter, a novel design of a branch-line coupler with considerable reduction in its size and suppressed harmonic passband is proposed. By embedding a defected ground structure (DGS) unit cell under a microstrip line, compact branch-line couplers are easily achieved. The electrical length is scaled appropriately according to the slow-wave effect. In this case, the experimental coupling (S21 or S31) is comparable to that of conventional branch-line couplers. Also, experimental results indicate that DGS section is quite effective for the suppression of higher order harmonics.

Although IP Multicast offers efficient data delivery for large group communications, the most critical issue delaying widespread deployment of IP Multicast is the scalability of multicast forwarding state as the number of multicast groups increases. Sender-Initiated Multicast (SIM) was proposed as an alternative multicast forwarding scheme for small group communications with incremental deployment capability. The key feature of SIM is in its Preset mode with the automatic SIM tunneling function, which maintaining forwarding information states only on the branching routers. To demonstrate how SIM increases scalability with respect to the number of groups, in this paper we evaluate the proposed protocol both through simulations and real experiments. As from the network operator's point of view, the bandwidth consumption, memory requirements on state-and-signaling per session in routers, and the processing overhead are considered as evaluation parameters. Finally, we investigated the strategies for incremental deployment.

This letter presents a reduction technique of penetrated electromagnetic fields through a narrow slot in a planar conducting screen. When a plane wave is excited to the narrow slot, the aperture electric field is controlled by the two parallel wires connected on the slot. The magnitude of penetrated electromagnetic fields through a narrow slot is controlled by electric field distributions on the slot aperture. The results show that the magnitude of the penetrated electromagnetic field can be effectively reduced by installing the two parallel wires on the slot.

Power consumption is a major concern in embedded microprocessors design. Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speed-critical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power. We evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is substantially energy-efficient while it suffers performance degradation.

A new Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) scheme is proposed to suppress leakage current by two orders of magnitude in the SRAM's for sub-70 nm process technology with sub-1-V VDD. This two-order leakage reduction is caused from the cooperation of reverse body-to-source biasing and Drain Induced Barrier Lowering (DIBL) effects. In addition, metal shields are proposed to be inserted between the cell nodes and the bit lines not to allow the cell nodes to be flipped by the external bit-line coupling noise in this paper. A test chip has been fabricated to verify the effectiveness of the RRDSV scheme with the metal shields by using 0.18-µm CMOS process. The retention voltages of SRAM's with the metal shields are measured to be improved by as much as 40-60 mV without losing the stored data compared to the SRAM's without the shields.

A noise reduction technique that uses the linear prediction to remove noise components in speech signals has been proposed previously. The noise reduction works well for additive white noise signals, because the coefficients of the linear predictor converge such that the prediction error becomes white. In this method, the linear predictor is updated by a gradient-based algorithm with a fixed step-size. However, the optimal value of the step-size changes with the values of the prediction coefficients. In this paper, we propose a noise reduction system using the linear predictor with a variable step-size. The optimal value of the step-size depends also on the variance of the white noise, however the variance is unknown. We therefore introduce a speech/non-speech detector, and estimate the variance in non-speech segments where the observed signal includes only noise components. The simulation results show that the noise reduction capability of the proposed system is better than that of the conventional one with a fixed step-size.

In this paper, we propose a new algorithm for calculating the exact poles of the admittance matrix of RLCG interconnects. After choosing dominant poles and corresponding residues, each element of the exact admittance matrix is approximated by partial fraction. A procedure to obtain the residues that guarantee the passivity is also provided, based on experimental studies. In the procedure the residues are calculated by using the least squares method so that the partial fraction matches each element of the exact admittance matrix in the frequency-domain. From the partial fraction representation, the asymptotic equivalent circuit models which can be easily simulated with SPICE are synthesized. It is shown that an efficient model-order reduction is possible for short-length interconnects.

This paper proposes a new robust adaptive processing algorithm that is based on the extended least squares (ELS) method with running spectrum filtering (RSF). By utilizing the different characteristics of running spectra between speech signals and noise signals, RSF can retain speech characteristics while noise is effectively reduced. Then, by using ELS, autoregressive moving average (ARMA) parameters can be estimated accurately. In experiments on real speech contaminated by white Gaussian noise and factory noise, we found that the method we propose offered spectrum estimates that were robust against additive noise.