As described in this paper, construction and blind estimation methods of phase sequences are proposed for subcarrier-phase control based peak-to-average power ratio (PAPR) reduction in low-density parity-check (LDPC)-coded orthogonal frequency division multiplexing (OFDM) systems. On the transmitter side, phase sequence patterns are constructed based on a given parity-check matrix. The PAPR of the OFDM signal is reduced by multiplying the constructed phase sequence selected from the same number of candidates as the number of weighting factor (WF) combinations in a partial transmit sequence (PTS) method. On the receiver side, the phase sequence is estimated blindly using the decoding function, i.e., the most likely phase sequence among a limited number of possible phase sequence candidates is inferred by comparing the sum-product calculation results of each candidate. Computer simulation results show that PAPR of QPSK-OFDM and 16QAM-OFDM signals can be reduced respectively by about 3.7 dB and 4.0 dB without marked degradation of the block error rate (BLER) performance as compared to perfect estimation in an attenuated 12-path Rayleigh fading condition.

This paper investigates the effect of several frequency modulation profiles on conducted-noise reduction in dc-dc converters with programmed switching controller. The converter is operated in variable frequency modulation regime. Twelve switching frequency modulation profiles have been studied. Some of the modulation data are prepared using MATLAB software, and others are generated online. Moreover, all the frequency profiles have been designed and implemented using FPGA and experimentally investigated. The experimental results show that the conducted-noise spreading depends on both the modulation sequence profile and the statistical characteristics of the sequence. A substantial part of the manufacturing cost of power converters for telecommunication applications involves designing filters to comply with the EMI limits. Considering this investigation significantly reduces the filter size.

Test data volume and test power are two major concerns when testing modern large circuits. Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying a single bit index and copying group data. In this paper, we propose an extended selective encoding which presents two new techniques to optimize this method: a flexible grouping strategy, X bits exploitation and filling strategy. Flexible grouping strategy can decrease the number of groups which need to be encoded and improve test data compression ratio. X bits exploitation and filling strategy can exploit a large number of don't care bits to reduce testing power with no compression ratio loss. Experimental results show that the proposed technique needs less test data storage volume and reduces average weighted switching activity by 25.6% and peak weighted switching activity by 9.68% during scan shift compared to selective encoding.

This paper treats a band-broadening design technique of a dual-band branch-line coupler with matching networks composed of an impedance step and a short-circuited stub based on the equivalent admittance approach. By replacing each right-handed transmission line (RH-TL) with a composite right/left-handed transmission line (CRLH-TL), very flat couplings over a relative bandwidth of about 10% can be obtained at two arbitrary operating frequencies in comparison with previous CRLH-TLs branch-line couplers. Furthermore, by adding periodical open-circuited stubs into RH-TLs of the designed CRLH-TLs branch-line coupler with matching networks, the entire size of the coupler can be reduced to about 50%. Verification of these band-broadening and size-reduction design techniques can be also shown by an electromagnetic simulation and experiment.

Acoustic feature transformation is widely used to reduce dimensionality and improve speech recognition performance. In this letter we focus on dimensionality reduction methods that minimize the average classification error. Unfortunately, minimization of the average classification error may cause considerable overlaps between distributions of some classes. To mitigate risks of considerable overlaps, we propose a dimensionality reduction method that minimizes the maximum classification error. We also propose two interpolated methods that can describe the average and maximum classification errors. Experimental results show that these proposed methods improve speech recognition performance.

We propose a new speech enhancement method suitable for mobile devices used in the presence of various types of noise. In order to achieve high-performance speech recognition and auditory perception in mobile devices, various types of noise have to be removed under the constraints of a space-saving microphone arrangement and few computational resources. The proposed method can reduce both the directional noise and the diffuse noise under the abovementioned constraints for mobile devices by employing a square microphone array and conducting low-computational-cost processing that consists of multiple null beamforming, minimum power channel selection, and Wiener filtering. The effectiveness of the proposed method is experimentally verified in terms of speech recognition accuracy and speech quality when both the directional noise and the diffuse noise are observed simultaneously; this method reduces the number of word errors and improves the log-spectral distances as compared to conventional methods.

This letter proposes a fast IP address lookup algorithm based on search space reduction. Prefixes are classified into three types according to the nesting relationship and a large forwarding table is partitioned into multiple small trees. As a result, the search space is reduced. The results of analyses and experiments show that the proposed method offers higher lookup and updating speeds along with reduced memory requirements.

A band-pass bilateral filter is an improved variant of a bilateral filter that does not have low-pass characteristics but has band-pass characteristics. Unfortunately, its computation time is relatively large since all pixels are subjected to Gaussian calculation. To solve this problem, we pay attention to a nonlinear filter called ε-filter and propose an advanced ε-filter labeled band-pass ε-filter. As ε-filter has low-pass characteristics due to spatial filtering, it does not enhance the image contrast. On the other hand, band-pass ε-filter does not have low-pass characteristics but has band-pass characteristics to enhance the image contrast around edges unlike ε-filter. The filter works not only as a noise reduction filter but also as an edge detection filter depending on the filter setting. Due to its simple design, the calculation cost is relatively small compared to the band-pass bilateral filter. To show the effectiveness of the proposed method, we report the results of some comparison experiments on the filter characteristics and computational cost.

In this paper, the scan chain ordering method for BIST-aided scan test for reducing test data and test application time is proposed. In this work, we utilize the simple LFSR without a phase shifter as PRPG and configure scan chains using the compatible set of flip-flops with considering the correlations among flip-flops in an LFSR. The method can reduce the number of inverter codes required for inverting the bits in PRPG patterns that conflict with ATPG patterns. The experimental results for some benchmark circuits are shown to present the feasibility of our test method.

An efficient multiplier design method for predetermined coefficient groups is presented based on the variation of canonic signed digit (CSD) encoding and partial product sharing. By applications to radix-24 FFT structure and the pulse-shaping filter design used in CDMA, it is shown that the proposed method significantly reduces the area, propagation delay and power consumption compared with previous methods.

This paper proposes an improved method that uses a K-means method to effectively reduce the ringing artifacts in a color moving picture. To apply this improved K-method, we set the number of groups for the process to two (K=2) in the three dimensional R, G, B color space. We then improved the R, G, B color value of all of the pixels by moving the current R, G, B color value of each pixel to calculated center values, which reduced the ringing artifacts. The results were verified by calculating the overshoot and the slope of the light luminance around the edges of test images that had been processed by the new algorithm. We then compared the calculated results with the overshoot and slope of the light luminance of the unprocessed image.

This paper proposes a novel crest factor reduction (CFR) algorithm applicable to currently deployed W-CDMA base stations. The peak-to-average ratio (PAR) reduction of the multiple carrier mixed signal, namely CFR, has been an issue in order to convey the benefit of using low-cost power amplifiers. The simple final clipping method (SFCM) as a conventional method has been widely utilized due to its simplicity and effectiveness. However, the SFCM degrades the adjacent channel leakage ratio (ACLR) characteristic as well as the signal quality indicated by either the error vector magnitude (EVM) or the peak code domain error (PCDE). Conventionally, in order to alleviate this undesired deterioration, extra channel filtering and signal quality enhancement followed by CFR might be processed in an open-loop style. Alternatively, to perform CFR by maintaining the PAR as low as possible subject to satisfying the prescribed ACLR and EVM/PCDE performance, this paper introduces the prediction filter dependent peak reduction (PFDPR) process collaboratively working with dynamic waterfilling-based code domain compensation (DWCDC). To verify the superiority of the proposed CFR algorithm, tentative simulations are conducted while maintaining the rules of legitimate W-CDMA base station test specifications.

In this paper, we present a novel analysis approach for large on-chip power grid circuit analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model order reduction techniques to reduce the circuit matrices before the simulation. Different from the (improved) extended Krylov subspace methods EKS/IEKS, ETBR performs fast truncated balanced realization on response Gramian to reduce the original system. ETBR also avoids the adverse explicit moment representation of the input signals. Instead, it uses spectrum representation in frequency domain for input signals by fast Fourier transformation. The proposed method is very amenable for threading-based parallel computing, as the response Gramian is computed in a Monte-Carlo-like sampling style and each sampling can be computed in parallel. This contrasts with all the Krylov subspace based methods like the EKS method, where moments have to be computed in a sequential order. ETBR is also more flexible for different types of input sources and can better capture the high frequency contents than EKS, and this leads to more accurate results especially for fast changing input signals. Experimental results on a number of large networks (up to one million nodes) show that, given the same order of the reduced model, ETBR is indeed more accurate than the EKS method especially for input sources rich in high-frequency components. If parallel computing is explored, ETBR can be an order of magnitude faster than the EKS/IEKS method.

In this paper, a new heuristic algorithm is proposed to optimize the power domain clustering in controlling-value-based (CV-based) power gating technology. In this algorithm, both the switching activity of sleep signals (p) and the overall numbers of sleep gates (gate count, N) are considered, and the sum of the product of p and N is optimized. The algorithm effectively exerts the total power reduction obtained from the CV-based power gating. Even when the maximum depth is kept to be the same, the proposed algorithm can still achieve power reduction approximately 10% more than that of the prior algorithms. Furthermore, detailed comparison between the proposed heuristic algorithm and other possible heuristic algorithms are also presented. HSPICE simulation results show that over 26% of total power reduction can be obtained by using the new heuristic algorithm. In addition, the effect of dynamic power reduction through the CV-based power gating method and the delay overhead caused by the switching of sleep transistors are also shown in this paper.

Scanning packet payload at a high speed has become a crucial task in modern network management due to its wide variety applications on network security and application-specific services. Traditionally, Deterministic finite automatons (DFAs) are used to perform this operation in linear time. However, the memory requirements of DFAs are prohibitively high for patterns used in practical packet scanning, especially when many patterns are compiled into a single DFA. Existing solutions for memory blow-up are making a trade-off between memory requirement and memory access of processing per input character. In this paper we proposed a novel method to drastically reduce the memory requirements of DFAs while still maintain the high matching speed and provide worst-case guarantees. We removed the duplicate transitions between states by dividing all the DFA states into a number of groups and making each group of states share a merged transition table. We also proposed an efficient algorithm for transition sharing between states. The high efficiency in time and space made our approach adapted to frequently updated DFAs. We performed several experiments on real world rule sets. Overall, for all rule sets and approach evaluated, our approach offers the best memory versus run-time trade-offs.

For phased and adaptive arrays of antennas, an optimal arrangement of antenna elements is essential to avoid grating lobes in the visible angular region of the array. Large sidelobes cause degradation in signal-to-noise ratio; grating lobes, in the worst case, cause malfunctions. One method of evaluating sidelobe level is square integration. For a given set element positions, evaluation by square integration of the sidelobes involves Fourier transform and numerical integration. For faster evaluation, we developed an equivalent transform algorithm that requires no numerical Fourier transform or integration. Using this new algorithm, we introduced a fast trial-and-error algorithm that iteratively applies random perturbation to the array, evaluates the function, and minimizes it. A number of separate runs of this algorithm have been conducted under the constraint of 3-fold rotational symmetry for stability. The optimal output, for which the function is minimized, is a uniformly spaced equilateral-triangular-type arrays that, unfortunately, has unwanted grating lobes. However the algorithm also yields variations trapped at local minima, some of which do not have grating lobes and whose sidelobe peaks are sufficiently low within a wide angular region. For the case N=12, a characteristic triagular-rectangular-type array often arises, which has not only better sidelobe properties as evaluated by square-integration and peak sidelobe, but also sufficient element-to-element clearance. For the case N=36, one of the results achieves a peak-sidelobe level of -8 dB, with a minimum element-to-element separation of 0.76 wavelength.

This investigation proposes two methods for embedding backdoors in the RSA modulus N=pq rather than in the public exponent e. This strategy not only permits manufacturers to embed backdoors in an RSA system, but also allows users to choose any desired public exponent, such as e=216+1, to ensure efficient encryption. This work utilizes lattice attack and exhaustive attack to embed backdoors in two proposed methods, called RSASBLT and RSASBES, respectively. Both approaches involve straightforward steps, making their running time roughly the same as that of normal RSA key-generation time, implying that no one can detect the backdoor by observing time imparity.

A reduced complexity quantization error correction method for lattice reduction aided (LRA) vector precoding is proposed. For LRA vector precoding,Babai's approximation procedure can generate quantization errors leading to performance loss. Instead of making a list to correct all possible errors as is done in the existing scheme, we propose a novel method in which only a subset of all possible errors are corrected. The size of the subset is determined by the probability distribution of the number of actual errors. Thus, the computation complexity of our correction procedure is reduced with little performance loss compared with the existing correction scheme.

One major drawback of orthogonal frequency-division multiplexing is the high peak-to-average power ratio (PAPR) of the output signal. The selected mapping (SLM) and partial transmit sequences (PTS) methods are two promising techniques for PAPR reduction. However, to generate a set of candidate signals, these techniques need a bank of inverse fast Fourier transforms (IFFT's) and thus require high computational complexity. In this paper, we propose two low-complexity multiplication-free conversion processes to replace the IFFT's in the SLM method, where each conversion process for an N-point IFFT involves only 3N complex additions. Using these proposed conversions, we develop several new SLM schemes and a combined SLM & PTS method, in which at least half of the IFFT blocks are reduced. Computer simulation results show that, compared to the conventional methods, these new schemes have approximately the same PAPR reduction performance under the same number of candidate signals for transmission selection.

Recently, Au et al. proposed a practical hierarchical identity-based encryption (HIBE) scheme and a hierarchical identity-based signature (HIBS) scheme. In this paper, we point out that there exists security weakness both for their HIBE and HIBS scheme. Furthermore, based on q-ABDHE, we present a new HIBE scheme which is proved secure in the standard model and it is also efficient. Compared with all previous HIBE schemes, ciphertext size as well as decryption cost are independent of the hierarchy depth. Ciphertexts in our HIBE scheme are always just four group elements and decryption requires only two bilinear map computations.