A frequently occurring subcircuit consists of a loop of a resistor (R), a field-effect transistor (FET), and a capacitor (C). The FET acts as a switch, controlled at its gate terminal by a clock voltage. This subcircuit may be acting as a sample-and-hold (S/H), as a passive mixer (P-M), or as a bandpass filter or bandpass impedance. In this work, we will present a useful analysis that leads to a simple signal flow graph (SFG), which captures the FET-R-C circuit's action completely across a wide range of design parameters. The SFG dissects the circuit into three filtering functions and ideal sampling. This greatly simplifies analysis of frequency response, noise, input impedance, and conversion gain, and leads to guidelines for optimum design. This paper focuses on the analysis of a single-path FET-R-C circuit's signal transfer characteristics including the reconstruction of the complete waveform from the discrete-time sampled voltage.

In this paper, the correspondence between the weighted line graph and the Mason signal flow graph (MSFG) has been established, which gives an interpretation of a convolutional network code (CNC) over a cyclic network from a different perspective. Furthermore, by virtue of Mason theorem, we present two new equivalent conditions to evaluate whether the global encoding kernels (GEKs) can be uniquely determined by the given complete set of local encoding kernels (LEKs) in a CNC over a cyclic network. These two new equivalent conditions turn out to be more intuitive. Moreover, we give an alternative simple proof of an existing result.

This paper presents a design of CMOS Chua-type analog chaos circuit by using a signal-flow-graph (SFG) method. In this circuit, the transmittance of a nonlinear element is realized by an OTA with a feedback resistor, and other linear elements are realized by op-amp based circuits. The proposed circuit is insensitive to the finite admittance of OTA's and to the parasitics of resistors except a feedback resistor in the nonlinear element. The performance and chaotic behavior of the proposed circuit are confirmed by SPICE simulations.

This paper proposes a parallel word alignment procedure for m Binary with 1 Complement Insertion (mBlC) or Differential m Binary with l Mark Insertion (DmBlM) line code. In the proposed procedure for mBlC line code, the word alignment circuit searches (m+1) bit pairs in parallel for complementary relationships. A Signal Flow Graph Model for the parallel word alignment procedure is also proposed, and its performance attributes are numerically analyzed. The attributes are compared with those of the conventional bit-by-bit procedure, and it is shown that the proposed procedure displays superior performance in terms of False-Alignment Probability and Maximum Average Aligning Time. The proposed procedure is suitable for high speed optical data links, because it can be easily implemented using a parallel signal processor operating at a clock rate equal to 1/(m+1) times the mBlC line rate.

On mutually coupling lines, the transmission signal is dispersively propagated by crosstalk coupling between lines and shows complex propagation characteristics caused by reciprocal reflections. Usually, the differential equation and the integral equation have been applied to analyze the solutions of transmission lines. In this paper, we propose a different analytical method of the propagation characteristics of signal and crosstalk noise. By setting up crosstalk coupling line as a sectionally divided digital transmission network and by using the signal flow graph and the difference equation, the propagation characteristics in the frequency domain, the space domain and the time domain on mutually coupling lines can be obtained. To verify the validity of this method and analyze the complex propagation problems, we first study the crosstalk characteristics of a twisted pair cable via the third circuit by unidirectional coupling. Subsequently we will analyze the coupling theory of bidirectional coupling lines.

In this paper, we present Branching Oriented System Equation based on-line error correction scheme for recursive digital signal processing. The target digital signal processing is linear and time-invariant, and the algorithm includes multiplications with constant coefficient, additions and delays. The difficulties of the algorithm-level fault tolerance for such algorithm without structural regularity include error distribution problem and right timing of error correction. To escape the error distribution problem, multiple fan-out nodes in an algorithm are specified as the nodes at which error corrections are performed. The Branching Oriented Graph and Branching Oriented System Equation are so introduced to formulate on-line correction schemes based on this strategy. The Branching Oriented Graph is treated as the collection of computation sub-blocks. Applying checksum code independently to each sub-block is our most trivial on-line error correction scheme, and it results in, with appropriate selection of error identification process, TMR in sub-block level. One of the advantages of our method is in the reduction of redundant operations performed by merging some computation sub-blocks. On the other hand, the schedulability of the system is an important issue for our method since our on-line error correction mechanism induces additional data dependencies. In this paper, the schedulability condition and some modifications on the scheme are also discussed.

Wave digital filters are a class of digital filters. They are equivalent to commensurate transmission line circuits synthesized with uniform, lossless, and commensurated transmission lines. In order to extend their applications to physical wave phenomena including quantum electronics, it is necessary to consider a generalized distributed line whose velocity of energy flow has frequency characteristics. This paper discusses a generalized distributed circuit, and we obtain two types of lines, lossless and cut-off. In order to analyze these lines, we discuss signal flow graphs of steady state voltage and current. The reflection factors we obtain here are the same as that for an active power or a diagonal element of a scattering matrix, which is zero in conjugate matching. By using this reflection factor, we obtain band-pass filters synthesized with the cut-off lines. We also describe an analysis method for nonuniform line related to Riccati differential equation.

This paper proposes a hierarchical Digital Signal Processor (DSP) Code Generator VIRGO for large scale general signal processing algorithms. Hierarchical structured Vectorized Signal Flow Graph (V-SFG) description is used as input specifications. Ths DSP independent optimization procedure for both the program size and the execution time is performed each module by each hierarchically with regard to operation order, memory assignment and register allocation. The efficient code generation is demonstrated by comparing both instruction steps and dynamic steps of a practical ADPCM encoder/decoder with a conventional method.