Available statistical skew models are too conservative in estimating the expected clock skew of a well-balanced H-tree. New closed form expressions are presented for accurately estimating the expected values and the variances of both the clock skew and the largest clock delay of a well-balanced H-tree. Based on the new model, clock period optimizations of wafer scale H-tree clock network are investigated under both conventional clocking mode and pipelined clocking mode. It is found that when the conventional clocking mode is used, clock period optimization of wafer scale H-tree is reduced to the minimization of expected largest clock delay under both area restriction and power restriction. On the other hand, when the pipelined clocking mode is considered, the optimization is reduced to the minimization of expected clock skew under power restriction. The results obtained in this paper are very useful in the optimization design of wafer scale H-tree clock distribution networks.

In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such that a clock-input timing of each register is a multiple of a predefined unit delay and the wire length from a clock buffer to an element driven by it is bounded. The clock trees are constructed for several practical circuits. The size of constructed clock tree is comparable to a zero skew clock tree. In order to assure the practical quality of the clock trees, they are examined under the five delay conditions, which cover various environmental and manufacturing conditions. As a result, they are proved stable under each condition and improve the clock speed up to 17.3% against the zero skew clock trees.

Skew angle effects on the transition noise are analyzed in the longitudinal disk media by micromagnetic simulations at area densities from 14.3 Gb/in2 to 31.5 Gb/in2. The transition noise, including the peak, width and jitter noise, is the dominant noise in ultra-high density disk recording systems. An isotropic medium and an oriented medium, with a fixed grain size of 135 and a coercivity of 2900 Oe, are chosen for the noise analysis. The peak noise is studied by the distribution of the peak magnetization amplitude Mp in each bit. The transition a-parameter is no longer the value as given in the William-Comstock approximation. It is found that the transition noise is highly dependent on both the linear den sity and the skew angle, where the bit length and the grain size are on the same order. In both media, the medium noise increases severely when the skew angle is above 10 degrees.

Large amounts of color-printed documents are published now everyday. Some OCR approaches of color-printed document images are provided, but they cannot normally work if the input images skew. In the past years, many algorithms are provided to detect the skew of monochrome document images but none of them process color-printed document images. All of these methods assume that text is printed in black on a white background and cannot be applied to detect skew in color-printed document images. In this paper, we propose an algorithm to detect the skew angle of a color-printed document image and reconstruct it. Our approach first determines variation of color-transition count at each angle (from -45 to +45) and the angle of maximal variation is regarded as the skew angle. Then, a scanning-line model reconstructs the image. We test 100 color-printed document images of various kinds and get good results (93 succeed and 7 fail). The average processing time of A4 size image is 2.76 seconds and the reconstruction time is 3.97 seconds on a Pentium III 733 PC.

As the clock skew is one of the major constraints for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization may increase the total wire length; therefore, clock routing is performed within the given skew bound. Clock routing under the specified skew bound can decrease the total wire length. A new efficient algorithm for bounded clock skew routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevents the total wire length from increasing. Not only the total wire length and delay time minimization algorithm using the new merging point relocation method but also the clock skew reduction algorithm using link-edge insertion technique for a pair of nodes whose delay difference is large is proposed. The proposed algorithm constructs a new clock routing topology which is a generalized graph model, while most previous methods use only tree-structured routing topology. A new cost function is designed in order to select two nodes for link-edge addition. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance is small. Furthermore, routing topology construction and wire sizing algorithm is used to reduce the clock delay. The proposed algorithm is implemented in C programming language. The experimental results show that the total wire length can be reduced under the given skew bound.

Graph products have important role in constructing many useful networks. It is known that there are four basic graph products. Properties of each product have been studied individually. We propose a unified approach to these products based on the distance in graphs, and new two products on graphs. The viewpoint of products based on the distance introduced here provides a family of products that includes almost known graph products as extremal ones and suggests new products. Also,we study relations among these six products. Finally, we investigate several classes of graph products in those context.

We have developed a low-latency, error-correcting-code-(ECC-)adaptable skew-compensation technique, which is needed for high-speed and long-distance parallel optical interconnections. A new frame-coding technique called shuffled mB1C encoding, which requires no clock-rate conversion circuit and no data buffering, and a new skew-measurement method which is suitable for ECC adaptation have been developed for the compensation. Full-digital skew-compensation circuits using these new techniques were able to compensate for a two-clock-cycle skew, even when one transmission channel was removed. The maximum latency for skew compensation was only five clock cycles.

We have developed a low-latency, error-correcting-code-(ECC-)adaptable skew-compensation technique, which is needed for high-speed and long-distance parallel optical interconnections. A new frame-coding technique called shuffled mB1C encoding, which requires no clock-rate conversion circuit and no data buffering, and a new skew-measurement method which is suitable for ECC adaptation have been developed for the compensation. Full-digital skew-compensation circuits using these new techniques were able to compensate for a two-clock-cycle skew, even when one transmission channel was removed. The maximum latency for skew compensation was only five clock cycles.

This paper describes a wide-frequency-range phase-locked-loop (PLL) clock generator embedded in a gate array LSI using 0.25 µm CMOS/SIMOX technology. The four ratios of internal clock frequency to external clock frequency this generator supports are 2, 4, 8, and 16. The PLL has two kinds of voltage-controlled oscillators that are selected automatically according to the frequency so as to widen the operating frequency range while keeping jitter low. Measured results show that the PLL operates with a lock range from 5 to 500 MHz. At 500 MHz, the peak-to-peak jitter is 50 ps. The supply voltage is 2 V and power dissipation is less than 14 mW. At a supply voltage of 2 V, the maximum operating frequency of 0.25 µm CMOS/SIMOX PLL is 30% higher than that of 0.25 µm bulk CMOS PLL.

It becomes essential in practice to improve a processing rate and to divide an image into small segments adjusting a limited memory, because image filing systems handle large images up to A1 size. This paper proposes a new method of an automatic skew normalization, comprising a high-speed skew detection and a distortion-free dividing rotation. We have evaluated the proposed method from the viewpoints of the processing rate and the accuracy for typed documents. As results, the processing rate is 2. 9 times faster than that of a conventional method. A practical processing rate for A1 size documents can be achieved under the condition that the accuracy of a normalized angle is controlled within 0. 3 degrees. Especially, the rotation with dividing can have no error angle, even when the A1 size documents is divided into 200 segments, whereas the conventional method cause the error angle of 1. 68 degrees.

This paper describes a low-skew clock distribution technique for multiple targets. An automatic skew compensation circuit, that detects the round-trip delay through a pair of matched interconnection lines and corrects the delay of the variable delay lines, maintains clock skew and delay from among multiple targets below the resolution time of the variable delay lines without any manual adjustment. Measured results show that the initial clock skew of 900 ps is automatically reduced to 30 ps at a clock frequency of up to 250 MHz with 60 ps of clock jitter. Moreover, they show that the initial clock delay of 1500 ps is cancelled and 60 ps of clock delay can be achieved. The power dissipation is 100 mW at 250 MHz.

We present a scalable parallel memory architecture with a skew scheme by which permanent-concentration-free strides, if any, do not depend on the number of ways in parallel memory interleaving. The permanent-concentration is a kind of memory access conflict. With conventional skew schemes, permanent-concentration-free strides depended on the number of banks (or bank groups) in parallel memory (=number of ways in parallel memory interleaving). We analyze two kinds of cause of conflicts: permanent-concentration occurs when memory access requests concentrate in limited number of banks (or bank groups) in parallel memory, and transient-concentration, when memory access requests transiently concentrate in some banks (or bank groups) in parallel memory. We have identified permanent-concentration-free strides, which are independent of the number of banks (or bank groups) in parallel memory, by solving two concentrations separately. The strategy is to increase the size of address block of shifting address assignment to the parallel memory in order to reduce permanent-concentrations, and make the size of the buffer for each banks (or bank groups) in the parallel memory match the size of address block of shifting in order to absorb transient-concentrations. The skew scheme uses the same size of address block of shifting address assignment for memory systems for different numbers of banks (or bank groups) in parallel memory. As a result, scalability for permanent-concentration-free strides is achieved independent of the number of banks (or bank groups) in parallel memory.

This paper presents a clock routing technique called Balanced-Mesh Method (BMM) which incorporates the advantages of two famous conventional-clock-routing techniques. One is the balanced-tree method (BTM) where the clock net is routed as a tree so that the delay times of clock signal are balanced, and the other is the fixed-mesh method (FMM) where the clock net is routed as a fixed mesh driven by a large buffer. In BMM, the clock net is routed as a set of relatively small meshes of interconnects driven by relatively small buffers. Each mesh covers an area called a Mesh-Routing Region (MR) in which its delay and skew can be suppressed within a certain range. These small meshes are connected by a balanced tree with the chip clock source as its root. To implement BMM, we developed an MR-partitioning program that partitions the circuit into MR's according to a set of pre-determined constraints on the number of flip-flops and the area in each MR, and a clock-global-routing program that provides each mesh routing and the tree routing connecting meshes. We applied BMM to the design of an MPEG2-encoder LSI and achieved a skew of 210ps. In addition, the experimental results show BMM yields the lowest power dissipation compared to conventional methods.

This paper presents a novel clock routing method used in constructing an optimal clock tree for embedded array chips by determining the route so as to minimize both delay and skew. The proposed method features constructing a tree by optimal node-pair merging, predicting the upper side balancedtree structure, based on accurate global path or delay estimation. By this method, in the case of the chip with large macro cells, the delay estimation error has been within 10%.

We report two new timing control methods for high-speed synchronous interfaces in view of their application to high-speed synchronous DRAMs. These two new circuits are the measure-controlled DLL and the register-controlled DLL.We quantitatively analyzed the minimum operational cycle time for a synchronous interface, and related the minimum bus cycle time to two factors; the bus-to-clock timing skew, and the unit delay time of the DLL. Based on this analysis, we concluded that the I/O performance can be beyond 400 MHz by suppressing both factors to less than 200 ps.