Knowledge-based Database Assistant is an expert system designed to help novice users formulate correct and complete database queries. This paper describes a knowledge-based database assistant with advanced facilities such as (1) a menu-based querymaking guidance, (2) a menu-based natural-language user-interface, and (3) database-commands generator which formulates formal database queries with SQL language. The system works as an intelligent front-end to an SQL database system or a computer-aided SQL tutorial-system. In this paper, we also discuss a semantic-network model, named S-Net, which is used to represent the knowledge for formal database-query formulating processes. The menu-based English user-interface allows end-users to make a query by filling a certain query pattern with appropriate words. The query-pattern filling process is guided by pop-up menus provided by the system. The query-pattern instances thus obtained are then translated into formal database queries. The translation is carried out by evaluating operations on S-Net knowledge-base which conveys knowledge about application domain, and the underlying database schema.

In the future, it will be necessary that robot technology or environmental technology has an auditory function of recognizing sound expect for speech. In this letter, we propose a recognition system for the species of birds receiving birdcalls, based on network technology. We show the first step of a recognition system for the species of birds, as an application of a recognition system for environmental sound.

For each two positive integers r, s, let [1DCM(r)-Time(ns)] ([1NCM(r)-Time(ns)]) and [1DCM(r)-Space(ns)] ([1NCM(r)-Space(ns)]) be the classes of languages accepted in time ns and in space ns, respectively, by one-way deterministic (nondeterministic) r-counter machines. We show that for each X{D, N}, [1XCM(r)-Time(ns)][1XCM(r+1)-Time(ns)] and [1XCM(r)-Space(ns)][1XCM(r+1)-Space(ns)]. We also investigate the relationships between one-way multicounter machines and cooperating systems of one-way finite automata. In particular, it is shown that one-way (one-) counter machines and cooperating systems of two one-way finite automata are equivalent in accepting power.

The fast and highly reliable method reported here uses two techniques to detect all types of defects, such as unsoldered leads, solder bridges, and misalignes leads in the minute solder joints of high density mounted devices. One technique uses external force applied by an air jet that vibrates or shifts unsoldered leads. The vibration and shift is detected as a change in the speckle pattern produced by laser illumination of the solder joints. The other technique uses fluorescence generated by short-wavelength laser illumination. The fluorescence from a printed circuit board produces a silhouette of the solder joint and this image is processed to detect defects. Experimental results show that this inspection method detects all kinds of defects accurately and with a very low false alarm rate.

We often use data flow diagrams or state transition diagrams to design software systems with concurrency. We call those diagrams as nets in this paper. Semantics of any methods to describe such software systems should be defined in some formal ways. There would be no doubts that any nets should be supported by appropriate theoretical frameworks. In this paper, we use CCS as a typical algebraic approach of using formulas to express concurrent behaviors and point out the different features of CCS from Petri nets. Any approaches should be not only theoretically beautiful but also practically useful. We use a specification language LOTOS as such example which has two features, CCS and ADT, and is designed to specify practical communication protocols. Algebraic approaches of using formulas, like LOTOS, can be considered as a compact way to express concurrent behaviors. We explore our discussions of net-oriented approaches into UIMS research fields. After mentioning state transition models of UIMS, we exemplify a practically used example, VIA-UIMS, which has been developed by one of authors. VIA-UIMS employs a net-oriented architecture. It has been designed to reconstuct tools which have already been widely used in many sites.

High speed simulation of neural networks can be achieved through parallel implementations capable of exploiting their massive inherent parallelism. In this paper, we show how this inherent parallelism can be effectively exploited on parallel data-driven systems. By using these systems, the asynchronous parallelism of neural networks can be naturally specified by the functional data-driven programs, and maximally exploited by pipelined and scalable data-driven processors. We shall demonstrate the suitability of data-driven systems for the parallel simulation of neural networks through a parallel implementation of the widely used back propagation networks. The implementation is based on the exploitation of the network and training set parallelisms inherent in these networks, and is evaluated using an image data compression network.

As in other fields, the automatization of railway maintenance work is a firm requirement. The authors have developed a system detecting obstacles around a railway for practical railway inspection. The system is based on an original laser-sectioning method and characterized by high accuracy with wide view and in-motion operation. It was confirmed that a static calibration was performed at an accuracy of within 5 mm. Furthermore, a theoretical estimation predicted that dynamic errors can be eliminated within a resolution of 4 mm by means of rail movement detection. In field tests on the Chuo Line, facilities were successfully inspected at speeds up to 40km/h.

This article discusses on PDM (Petri net based Development Methodology) which integrates approaches, modeling methods, design methods and analysis methods in a coherent manner. Although various development techniques based on Petri nets have demonstrated advantages over conventional techniques, those techniques are rather ad hoc and lack an overall picture on entire development process. PDM anticipates to provide a refernce process model to develop distributed systems with various Petri net based development methods. Behavioral properties of distrbuted systems can be an appropriate application domain of PDM.

One of the most interesting and most analyzed aspects of the CPU design is the instruction set design. How many and which operations to be provided by hardware is one of the most fundamental issues relaing to the instruction set design. This paper describes a novel method that formulates the instruction set design of ASIP (an Application Specific Integrated Processor) using a combinatorial appoach. Starting with the whole set of all possible candidata instructions that represesnt a given application domain, this approach selects a subset that maximizes the performance under the constraints of chip area, power consumption, and functional module sharing relation among operations. This leads to the efficient implementation of the selected instructions. A branch-and-bound algorithm is used to solve this combinatorial optimization problem. This approach selects the most important instructions for a given application as well as optimizing the hardware resources that implement the selected instructions. This approach also enables designers to predict the perfomance of their design before implementing them, which is a quite important feature for producing a quality design in reasonable time.

A new Viterbi algorithm with adaptive path reduction method is presented. The proposed system consists of the pre-decoder and reduced path Virerbi decoder. The predecoder separates the mixed channel noise from the received sequence. The number of errors in the pre-decoded error sequence is counted and the path reduction is implemented by the number of errors in pre-decoded error sequence. The path reduction is implemented as a function of channel condition because the errors in the pre-decoded error sequence can be considered as the channel error sequence. Due to the reduction of the path, the number of ACS (add compare select) operations can be reduced, which occupies the dominant part in Viterbi decoding. The ACS reduction ratio for the proposed system achieves up to 30% for the case of (2, 1, 2) Ungerboeck code without degradation of the error performance.

This paper summarizes basic system design for an optical fiber feeder for microcellular mobile communication systems. The optical feeder enables compact and low cost base stations, easy radio channel control and flexible mobile communication systems. Basic transmission characteristics are investigated through optical transmission experiments. By using these results, feeder performance is estimated and optimal system parameters are designed.

The Princeton University Behavioral Synthesis System (PUBSS) performs high-level synthesis on communicating processes. The compiler accepts models written in a subset of VHDL, but performs synthesis using a more specialized model, the behavior FSMs (BFSMs), for synthesis. The simulation semantics of VHDL presents challenges in describing behavior without overly constraining that behavior solely to make the simulation work. This paper describes mismatch between the simulation semantics provided by VHDL and the synthesis semantics required for high-level synthesis and describes how we solved these problems in PUBSS.

A quantum interconnection scheme by controlling the Coulomb interaction between ballistic electrons is proposed in which 2DEG (2 dimensional electron gas) plays the role of an interconnection medium. This concept brings up new possibilities for the interconnection approach in various fields such as parallel processing, telecommunications switching, and quantum functional devices. Cross-over interconnection, address collision, and address selection in a quantum information network system were analyzed as the first step. The obtained results have shown that the interconnection probability can be controlled by the velocity and timing of the ballistic electron emission from the emitter electrode. The proposed interconnection scheme is expected to open up a new field of quantum effect integrated circuits in the 21st century.

In this paper, we investigate various technology aspects in fiber-to-the-microcell systems. Background studies on radio propagation environment and system operations are provided first. The fundamental linearity characteristics of a directly and externally modulated optical links are analyzed next. An overall comparison between the two types of optical links, and system requirements among all types of wireless systems (from macrocells to picocells) are presented. Future research and development directions are also suggested.

This paper reports performance improvement in an optical fiber feeder for microcellular mobile radio systems. A low noise optical receiver using a transformer resonant circuit is described. With this receiver, CNR degradation due to receiver noise is suppressed to less than 0.9dB. Furthermore, two novel techniques, the use of a multiple-LD transmitter and automatic LD input level control, are proposed. The multiple-LD transmitter increases transmitter output power and reduces the transmitter noise. With a dual-LD transmitter, it is possible to increase the optical loss margin by 3.1dB, which corresponds to transmission length expansion of 6.2km, or to improve the received CNR by 2.8dB, which enables communication range expansion. Automatic LD input level control, which optimizes LD input level according to the received radio power, can expand the actual dynamic range of the up link.

A new circuit design of Josephson ternary δ-gate composed of Josephson junction devices is presented. Mathematical theory for synthesizing, analyzing, and realizing any given function in ternary system using Josephson ternary δ-gate is introduced. The Josephson ternary δ-gate is realized using SQUID technique. Circuit simulation results using J-SPICE demonstrated the feasibility and the reliability operations of Josephson ternary δ-gate with very high performances for both speed and power consumption (max. propagation delay time44 ps and max. power consumption2.6µW). The Josephson ternary δ-gate forms a complete set (completeness) with the ternary constants (1, 0, 1). The number of SQUIDs that are needed to perform the operation of δ-gate is 6. Different design with less than 6 SQUIDs is not possible because it can not perform the operation of δ-gate. The advantages of Josephson ternary δ-gate compared with different Josephson logic circuits are as follows: The δ-gate has the property that a simple realization to any given ternary logic function as the building blocks can be achieved. The δ-gate has simple construction with small number of SQUIDs. The δ-gate can realize a large number of ternary functions with small number of input/output pins. The performances of δ-gate is very high, very low power consumption and ultra high speed switching operation.

In this paper we propose an architecture and an algorithm for the parallel execution of OPS5 production systems. It is known that current OPS5 production system interpreters spend almost 90% of their execution time in the match step. Thus, in this paper we focus on the speedup of the match step. The match algorithm used in OPS5 is called Rete and the algorithm uses a special kind of a date-flow network compiled from the left hand sides of rules. To achieve the maximum degree of parallelism of a given OPS5 program by as few processors as possible, the proposed parallel machine uses loosely coupled multiprocessors. Parallel machines designed for fine-grain parallelism, such as DADO, also use loosely coupled multiprocessors. However, the proposed machine differs from such machines at the following points: use of powerful processors which have large amounts of memories and small cycle times; use of a shared Rete network (parallel machines designed for fine-grain parallelism use an unshared Rete network); high hardware utilization. Basic ideas of the proposed parallel machine are as follows. (1) Use of a modified Rete network in which node sharing is used only for constant-test nodes and each memory node is lumped with the child two-input node. (2) Static allocation of the nodes of the modified Rete network onto processors. (3) Partition of the set of processors into three subsets: constant-test node processors, two-input node processors and conflict-set processors. (4) Use of a ring network for the interconnection network among two-input node processors. In addition to an architecture for parallel execution of OPS5 production systems, we propose a scheme for mapping the modified Rete network into the proposed architecture. The results of simulation experiments showed that the proposed architecture is promising for parallel execution of OPS5 production systems.

A new trial of statistical evaluation for an output response of power linear type acoustic systems with nonstationary random input is proposed. The purpose of this study is to predict the output probability distribution function on the basis of a standard type pre-experiment in a laboratoty. The statistical properties like nonstationarity, non-Gamma distribution property and various type linear and non-linear correlations of input signal are reflected in the form of differential operation with respect to distribution parameters. More concretely, the pre-experiment is carried out for a power linear acoustic system excited only by the Gamma distribution type sandard random input. Considering the non-negative random property for the output response of a power linear system, the well-known statistical Laguerre expansion series type probability expression is first employed as the framework of basic probability distribution expression on the output power fluctuation. Then, the objective output probability distribution for a non-stationary case can be easily derived only by successively employing newly introduced differential operators to this basic probability distribution of statistical Laguerre expansion series type. As an application to the actual noise environment, the proposed method is employed for an evaluation problem on the stochastic response probability distribution for an acoustic sound insulation system excited by a nonstationary input noise.

Industrial radio control systems require a high degree of safety and reliability even in operating environments where harsh interference conditions exist. In order to implement Spread Spectrum (SS) modulation techniques in industrial radio control systems, a hybrid Direct Sequence/Frequency Hopping (DS/FH) system with high speed synchronization capability was designed, implemented and evaluated. In this system, a digital matched filter was utilized for despreading the DS signal. By manipulating the despread signal and sensing the correlation peak, the frequency hopping circuit can operate without a special synchronizing circuit. The focus of this report is on an engineering sample created for the 900MHz band available as an ISM band in the U.S. In this sample, error correction code was integrated with the hybrid DS/FH which gives the system excellent narrow-band interference rejection properties and Code Division Multiple Access (CDMA) capabilities.

In this paper, we evaluate the sustained performance of the prototype SHD (Super High Definition) image processing system NOVI- HiPIPE, and discuss the requirements of a real-time SHD image processing system. NOVI- HiPIPE is a parallel DSP system with 128 PEs (Processing Elements), each containing one vector processor, and its peak performance is 15 GFLOPS. The measured performance of this system is at least 100 times higher than that of the Cray-2 (single CPU), but is still insufficient for real-time SHD image coding. When coding SHD moving images at 60 frames per second with the JPEG algorithm, the performance must be at least ten times faster than is now possible with NOVI- HiPIPE. To extract higher performance from a parallel processing system, the system architecture must be suitable for the implemented process. The advantages of NOVI- HiPIPE are its mesh network and high performance pipelined vector processor (VP), one of which is installed on each PE. When most basic SHD image coding techniques are implemented on NOVI- HiPIPE, intercommunication occurs only between directly connected PEs, and its cost is very low. Each VP can efficiently execute vector calculations. which occur frequently in image processing, and they increase the performance of NOVI- HiPIPE by a factor of from 20 to 100. In order to further improve the performance, the speed of memory access and bit operation must be increased. The next generation SHD image processing system must be built around the VP, an independent function block which controls memory access, and another block which executes bit operations. To support the input and output of SHD moving images and the inter-frame coding algorithms, the mesh network should be expanded into a 3D-cube.