We demonstrate a single-channel 1.28 Tbit/s-525 km transmission using OTDM of subpicosecond DQPSK signals. In order to cope with transmission impairments due to time-varying higher-order PMD, which is one of the major limiting factors in such a long-haul ultrahigh-speed transmission, we newly developed an ultrafast time-domain optical Fourier transformation technique in a round-trip configuration. By applying this technique to subpicosecond pulses, transmission impairments were greatly reduced, and BER performance below FEC limit was obtained with increased system margin.

A self-calibrating per-pin phase adjuster, which does not require any feedback from the slave chip and a multi-phase clock in the master and slave chips, is proposed for a high speed parallel chip-to-chip interface with a source synchronous double data rate (DDR) signaling. It achieves not only per-pin phase adjustment but also 90° phase shift of a strobe signal for a source synchronous DDR signaling. For this self-calibration, the phase adjuster measures and compensates the only relative mismatched delay among channels by utilizing on-chip time-domain reflectometry (TDR). Thus, variable delay lines, finite state machines, and a test signal generator are additionally required for the proposed phase adjuster. In addition, the power-gating receiver is used to reduce the discontinuity effect of the channel including parasitic components of chip package. To verify the proposed self-calibrating per-pin phase adjuster, the transceivers with 16 data, strobe, and clock signals for the interface with a source synchronous DDR signaling were implemented by using a 60 nm 1-poly 3-metal CMOS DRAM process with a 1.5 V supply. Each phase skew between Strobe and 16 Data was corrected within 0.028UI at 1.6-Gb/s data rate in a point-to-point channel.

In wireless sensor networks, real-time data delivery schemes typically achieve the desired delivery speed by proactively performing one-hop lookahead. Recently, to reduce the deadline miss ratio with respect to the desired delivery speed, a study has proposed a real-time data delivery scheme based on proactively performing two-hop lookahead. However, the recent proposal might cause heavy message exchange overhead and high computing complexity in order to proactively obtain two-hop neighbor speed information in all sensor nodes whether data are delivered or not. In this paper, we propose a novel real-time data delivery scheme that applies on-demand multi-hop lookahead only around data forwarding paths. Hence, the scheme can provide lower deadline miss ratio for real-time data delivery with low message exchange overhead than existing schemes.

A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P + poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and > 100-ms data retention time under the condition of sub-1-V operating voltage.

A novel computational method is proposed to investigate electromagnetic scattering problems. It is error controllable and reliable simulation in time domain can be performed. We apply the proposed method to analysis of transient scattering from open-ended structures and discuss scattering mechanisms.

Wireless sensor networks represent a new data collection paradigm in which expandability plays an important role. In a practical monitoring environment, for example, food factory monitoring system, sensor relocations and reorganizations are necessary with reorganization of production lines and starting of new production lines. These relocations sometime make congestion in some area of the network. In this dynamic changing environment online expansion is a challenging problem for resource constraint network. This paper proposes a two-tier autonomous decentralized community architecture for wireless sensor network to solve the problem. The first layer consists of sensors and second layer consists of routers. In the architecture routers make community (a group of nodes mutually cooperate for a common goal is a community). The goal of this paper is to introduce the concept of sharing information among routers of the community to decrease sensor connection time for the network especially for the dynamic changing environment. Results show that our proposed technologies can reduce sensor connection time to achieve online expansion.

In this paper, we design a practical time-reversal quasi-orthogonal space-time block code (TR-QO-STBC) system for broadband multi-input multi-output (MIMO) communications. We first modify the TR-QO-STBC encoding structure so that the interference between the transmitted blocks can be completely removed by linear processing. Two low complex decision-feedback equalization (DFE) schemes are then proposed. One is built from the frequency-domain decision-feedback equalization (FD-DFE). The derived bi-directive FD-DFE (BiD-FD-DFE) cancels the interference among the successive symbols along the time axis. The other one is the enhanced V-BLAST, which cancels the interference between the real and imaginary parts of the spectral components. They have distinct performance characteristics due to the different interference-cancellation strategies. The underlying orthogonal and symmetric characters of TR-QO-STBC are exploited to reduce the computational complexity. Computer simulations confirm that the proposed equalizers can achieve better performance than the existing schemes.

The turn of the century is witnessing radical changes in the way information services are spreading due to the progress of IT and the constantly increase in the number of users of the WWW. Therefore, the business market is changing its strategy for a modern online business environment. Autonomous Decentralized Database System (ADDS), based on autonomous coordinating subsystems, has been proposed as a system architecture in order to meet the innovative e-business requirements for consistency and high response among distributed database systems. Autonomy and decentralization of subsystems help achieving high response time in highly competitive situation and autonomous Mobile Agent based coordination has been proposed to achieve flexibility in a highly dynamic environment. In this paper, it is analyzed the case in which the system size increases; and a multi agent coordination, the same number of mobile agents and sites coexist in the system, is proposed for achieving the timeliness property. The response time in the system is conformed by those transactions that require coordination and those that can be satisfied immediately. In accordance, the distribution of the data in the system for coordination is a medullar issue for the improvement of the response time. A trade-off exits between these two kind of transactions depending on the coordination of the Mobile Agents, the capacity of allocating data among the sites, and as well as the distribution of the data and user requests in the system. In this sense, since the system requires high response time, a data allocation technology in which each mobile agent autonomously determine its own capacity for adjusting data among the sites is proposed. Thus, the system will adapt itself to the dynamic environment. The effectiveness of the proposed architecture and technologies are evaluated by simulation.

In terrain visualization, the quadtree is the most frequently used data structure for progressive mesh generation. The quadtree provides an efficient level of detail selection and view frustum culling. However, most applications using quadtrees are performed on the CPU, because the pointer and recursive operation in hierarchical data structure cannot be manipulated in a programmable rendering pipeline. We present a quadtree-based terrain rendering method for GPU (Graphics Processing Unit) execution that uses vertex splitting and triangle splitting. Vertex splitting supports a level of detail selection, and triangle splitting is used for crack removal. This method offers higher performance than previous CPU-based quadtree methods, without loss of image quality. We can then use the CPU for other computations while rendering the terrain using only the GPU.

A novel random number generation method based on chaotic sampling of regular waveform is proposed. A high speed IC truly random number generator based on this method is also presented. Simulation and experimental results, verifying the feasibility of the circuit, are given. Numerical binary data obtained according to the proposed method pass the four basic tests of FIPS-140-2, while experimental data pass the full NIST-800-22 random number test suite without post-processing.

To reduce the inaccuracy caused by inappropriate time window, we propose two probabilistic fault localization schemes based on the idea of "extending time window." The global window extension algorithm (GWE) uses a window extension strategy for all candidate faults, while the on-demand window extension algorithm (OWE) uses the extended window only for a small set of faults when necessary. Both algorithms can increase the metric values of actual faults and thus improve the accuracy of fault localization. Simulation results show that both schemes perform better than existing algorithms. Furthermore, OWE performs better than GWE at the cost of a bit more computing time.

Wireless Sensor Network(WSN) is widely used in Emergency Management System(EMS) to assure high safety. Real-timely transmitting emergency information in dynamically changing environment should be assured in mission critical district. Conventional methods based on static situations and centralized approaches can not satisfy this requirement. In this paper, to assure real-time property, autonomous community construction technology is proposed to set special area called community which includes a special passage composed of several routers for emergency information's transmission and routers around this passage in one hop range. Emergency information's transmission is protected by routers around this passage from interference of other sensing information's transmission in and outside community. Moreover, autonomous community reconstruction technology is proposed to guarantee real-time property at failure conditions. In this technology, community members autonomously cooperate and coordinate with each other to setup a bypass in community for transmitting emergency information if fault happens. Evaluation results indicate effectiveness of proposed technology.

This paper proposes a new kind of communication system for air traffic control over the oceans; it is particularly effective at handling high air traffic loads due to many oceanic flights. In this system, each aircraft position report is sent to its relevant ground station by forwardly relaying them via a multi hop ad-hoc network that is formed by the aircraft between this aircraft and the ground station. In addition, an effective multiple access scheme with optimal values is also proposed. This scheme enables the various aircraft involved in relaying the signal to operate autonomously in a flight-route airspace. Furthermore, two useful schemes are proposed for efficient timeslot reuse and timeslot assignment in cases of low aircraft densities: the position aided timeslot reuse (PATR) and distance based timeslot assignment (DBTA), respectively. Finally, another scheme is proposed to improve the achievable relayed packet rate under low aircraft densities, which is called interference-based node selection (IB-NS). In all, the proposed system combined with those three schemes show the availability to utilize this system for air traffic control communications, specifically on high traffic ocean routes.

A two-dimensional filter for photonic label recognition system using time-to-space conversion and delay compensation was designed using Genetic-Algorithms (GA). For four-bit Binary Phase Shift Keying (BPSK) labels at 160 Gbit/s, contrast ratio of the output for eight different labels was improved by optimization of two-dimentional filtering. The contrast ratio of auto-correlation to cross-correlation larger than 2.16 was obtained by computer simulation. This value is 22% larger than the value of 1.77 with the previously reported system using matched filters.

In this paper, two techniques for implementing a low-power pipelined analog-to-digital converter (ADC) are proposed. First, the time-interleaved correlated double sampling (CDS) technique is proposed to compensate the finite gain error of operational amplifiers in switched-capacitor circuits without a half-rate front-end sample-and-hold amplifier (SHA). Therefore, low-gain amplifiers and the SHA-less architecture can be used to effectively reduce power consumption of a pipelined ADC. Second, the back-end pipelined stages of a pipelined ADC are implemented using a low-power time-interleaved successive approximation (SA) ADC rather than operational amplifiers to further reduce the power consumption of the proposed pipelined ADC. A 9-bit, 100-MS/s hybrid pipelined-SA ADC is implemented in the TSMC 0.13 µm triple-well 1P8M CMOS process. The ADC achieves a spurious free dynamic range (SFDR) of 62.15 dB and a signal-to-noise distortion ratio (SNDR) of 50.85-dB for 2-MHz input frequency at a 100-MS/s sampling rate. The power consumption is 21.2 mW from a 1.2 V supply. The core area of the ADC is 1.6 mm2.

A hardware description languages (HDLs) based modeling technique for asynchronous circuits is presented in this paper. A HDLs handshake package has been developed for expressing handshake-style digital systems in both VHDL and Verilog. Burst-mode and extended burst-mode (BM/XBM) circuits were used to demonstrate the usefulness of this work. This research successfully prototyped comparators, adders, RSA encoder/decoder, and several self-timed circuits for the full-custom IC and FPGAs designs. Furthermore, the HDLs handshake package implemented by this research can be utilized to develop behavioral test benches for studying and analyzing asynchronous designs. Extracting detailed timing information from asynchronous finite state machines (AFSMs), detecting delay faults for synthesized self-timed functional modules, and locating fundamental mode violation within realized AFSMs are proven applications. The anticipated HDL modeling technique and the transformation procedure are detailed in the rest of this paper.

In an embedded control system, control performances of each job depend on its latency and a control algorithm implemented in it. In order to adapt a job set to optimize control performances subject to schedulability, we design several types of control software for each job, which will be called versions, and select one version from them when the job is released. A real-time system where each job has several versions is called a multiversion real-time system. A benefit and a CPU utilization of a job depend on the versions. So, it is an important problem to select a version of each job so as to maximize the total benefit of the system subject to a schedulability condition. Such a problem will be called an optimal configuration problem. In this paper, we assume that each version is specified by the relative deadline, the execution time, and the benefit. We show that the optimal configuration problem is transformed to a maximum path length problem. We propose an optimal algorithm based on the forward dynamic programming. Moreover, we propose sub-optimal algorithms to reduce computation times. The efficiencies of the proposed algorithms are illustrated by simulations.

An antidictionary is particularly useful for data compression, and on-line electrocardiogram (ECG) lossless compression algorithms using antidictionaries have been proposed. They work in real-time with constant memory and give better compression ratios than traditional lossless data compression algorithms, while they only deal with ECG data on a binary alphabet. This paper proposes on-line ECG lossless compression for a given data on a finite alphabet. The proposed algorithm gives not only better compression ratios than those algorithms but also uses less computational space than they do. Moreover, the proposed algorithm work in real-time. Its effectiveness is demonstrated by simulation results.

This paper proposes approaches to perform HW/SW (Hardware/Software) partition and parallelization of computing-intensive tasks of the H.264 HiP (High Profile) decoding algorithm on an embedded coarse-grained reconfigurable multimedia system, called REMUS (REconfigurable MUltimedia System). Several techniques, such as MB (Macro-Block) based parallelization, unfixed sub-block operation etc., are utilized to speed up the decoding process, satisfying the requirements of real-time and high quality H.264 applications. Tests show that the execution performance of MC (Motion Compensation), deblocking, and IDCT-IQ (Inverse Discrete Cosine Transform-Inverse Quantization) on REMUS is improved by 60%, 73%, 88.5% in the typical case and 60%, 69%, 88.5% in the worst case, respectively compared with that on XPP PACT (a commercial reconfigurable processor). Compared with ASIC solutions, the performance of MC is improved by 70%, 74% in the typical and in the worst case, respectively, while those of Deblocking remain the same. As for IDCT_IQ, the performance is improved by 17% no matter in the typical or worst case. Relying on the proposed techniques, 1080p@30 fps of H.264 HiP@ Level 4 decoding could be achieved on REMUS when utilizing a 200 MHz working frequency.

This paper describes an affine motion estimation processor for real-time video segmentation. The processor estimates the dominant motion of a target region with affine parameters. The processor is based on the Pseudo-M-estimator algorithm. Introduction of an image division method and a binary weight method to the original algorithm reduces data traffic and hardware costs. A pixel sampling method is proposed that reduces the clock frequency by 50%. The pixel pipeline architecture and a frame overlap method double throughput. The processor was prototyped on an FPGA; its function and performance were subsequently verified. It was also implemented as an ASIC. The core size is 5.05.0 mm2 in 0.18 µm process, standard cell technology. The ASIC can accommodate a VGA 30 fps video with 120 MHz clock frequency.