In this paper, we proposed a novel two-stage channel estimation (2S-CE) method. In contrast to conventional channel estimation methods, this method makes the maximum use of the information contributed by the known data in every transmission burst. In the first stage, the least-squares (LS) algorithm was used to estimate the channel impulse response (CIR) based on the normal training sequence. Then the maximum channel memory was estimated and used to locate the uncorrupted data in the guard interval. In the second stage, the uncorrupted data together with the normal training sequence were sent to the LS algorithm again to obtain the fine-tuned CIR. To verify the efficiency of the proposed 2S-CE method, both a theoretical analysis and computer simulations have been done. Computer simulation results confirm the analysis results and demonstrate that the proposed 2S-CE method outperforms a conventional single-stage channel estimation method.

Supersingular isogeny Diffie-Hellman (SIDH) is attractive for its relatively small public key size, but it is still unsatisfactory due to its efficiency, compared to other post-quantum proposals. In this paper, we focus on the performance of SIDH when the starting curve is E6 : y2 = x3 + 6x2 + x, which is fixed in Round-3 SIKE implementation. Inspired by previous works [1], [2], we present several tricks to accelerate key generation of SIDH and each process of SIKE. Our experimental results show that the performance of this work is at least 6.09% faster than that of the SIKE implementation, and we can further improve the performance when large storage is available.

Conventional orthogonal frequency division multiplexing (OFDM) system utilizes cyclic prefix (CP) to remove the channel-induced inter-symbol interference (ISI) at the cost of lower spectral efficiency. In this paper, a generalized sidelobe canceller (GSC) based equalizer for ISI suppression is proposed for uplink multi-antenna OFDM systems without CP. Based on the block representation of the CP-free OFDM system, there is a natural formulation of the ISI suppression problem under the GSC framework. By further exploiting the signal and ISI signature matrix structures, a computationally efficient partially adaptive (PA) implementation of the GSC-based equalizer is proposed for complexity reduction. The proposed scheme can be extended for the design of a pre-equalizer, which pre-suppresses the ISI and realizes CP-free downlink transmission to ease the computational burden of the mobile unit (MU). Simulation results show that the proposed GSC-based solutions yield equalization performances almost identical to that obtained by the conventional CP-based OFDM systems and are highly resistant to the increase in channel delay spread.

The wavelet transform (WT) has recently emerged as a powerful tool for image compression. In this paper, a new image compression technique combining the genetic algorithm (GA) and grey-based competitive learning network (GCLN) in the wavelet transform domain is proposed. In the GCLN, the grey theory is applied to a two-layer modified competitive learning network in order to generate optimal solution for VQ. In accordance with the degree of similarity measure between training vectors and codevectors, the grey relational analysis is used to measure the relationship degree among them. The GA is used in an attempt to optimize a specified objective function related to vector quantizer design. The physical processes of competition, selection and reproduction operating in populations are adopted in combination with GCLN to produce a superior genetic grey-based competitive learning network (GGCLN) for codebook design in image compression. The experimental results show that a promising codebook can be obtained using the proposed GGCLN and GGCLN with wavelet decomposition.

Emerging video surveillance technologies are based on foreground detection to achieve event detection automatically. Integration foreground detection with a modern multi-camera surveillance system can significantly increase the surveillance efficiency. The foreground detection often leads to high computational load and increases the cost of surveillance system when a mass deployment of end cameras is needed. This paper proposes a DSP-based foreground detection algorithm. Our algorithm incorporates a temporal data correlation predictor (TDCP) which can exhibit the correlation of data and reduce computation based on this correlation. With the DSP-oriented foreground detection, an adaptive frame rate control is developed as a low cost solution for multi-camera surveillance system. The adaptive frame rate control automatically detects the computational load of foreground detection on multiple video sources and adaptively tunes the TDCP to meet the real-time specification. Therefore, no additional hardware cost is required when the number of deployed cameras is increased. Our method has been validated on a demonstration platform. Performance can achieve real-time CIF frame processing for a 16-camera surveillance system by single-DSP chip. Quantitative evaluation demonstrates that our solution provides satisfied detection rate, while significantly reducing the hardware cost.

Traditional face swapping technologies require that the faces of source images and target images have similar pose and appearance (usually frontal). For overcoming this limit in applications this paper presents a pose-free face swapping method based on personalized 3D face modeling. By using a deformable 3D shape morphable model, a photo-realistic 3D face is reconstructed from a single frontal view image. With the aid of the generated 3D face, a virtual source image of the person with the same pose as the target face can be rendered, which is used as a source image for face swapping. To solve the problem of illumination difference between the target face and the source face, a color transfer merging method is proposed. It outperforms the original color transfer method in dealing with the illumination gap problem. An experiment shows that the proposed face reconstruction method is fast and efficient. In addition, we have conducted experiments of face swapping in a variety of scenarios such as children's story book, role play, and face de-identification stripping facial information used for identification, and promising results have been obtained.

With the development of network technology, next-generation networks must satisfy many new requirements for network functions and performance. The processing of overlong packet fields is one of the requirements and is also the basis for ID-based routing and content lookup, and packet field addition/deletion mechanisms. The current SDN switches do not provide good support for the processing of overlong fields. In this paper, we propose a series of optimization mechanisms for protocol-oblivious instructions, in which we address the problem of insufficient support for overlong data in existing SDN switches by extending the bit width of instructions and accelerating them using SIMD instruction sets. We also provide an intermediate representation of the protocol-oblivious instruction set to improve the efficiency of storing and reading instruction blocks, and further reduce the execution time of instruction blocks by preprocessing them. The experiments show that our approach improves the performance of overlong data processing by 56%. For instructions involving packet field addition and deletion, the improvement in performance reaches 455%. In normal forwarding scenarios, our solution reduces the packet forwarding latency by around 30%.

This paper proposes a channel estimation technique which uses a postfixed pseudo-noise (PN) sequence combined with zero padding to accurately estimate the channel impulse response for mobile orthogonal frequency division multiplexing (OFDM) communications. The major advantage of the proposed techniques is the periodical insertion of PN sequences after each OFDM symbol within the original guard interval in conventional zero-padded OFDM or within the original cyclic prefix (CP) in conventional CP-OFDM. In addition, the proposed technique takes advantage of null samples padded after the PN sequences for reducing inter-symbol interference occurring with the information detection in conventional pseudo-random-postfix OFDM. The proposed technique successfully applies either (1) least-squares algorithm with decision-directed data-assistance, (2) approximate least-squares estimation, or (3) maximum-likelihood scheme with various observation windows for the purpose of improving channel estimation performance. Some comparative simulations are given to illustrate the excellent performance of the proposed channel estimation techniques in mobile environments.

This paper proposes an improved discrete Fourier transform (DFT)-based channel estimation technique for time domain synchronous orthogonal frequency division multiplexing (TDS-OFDM) communication systems. The proposed technique, based on the concept of significant channel tap detector (SCTD) scheme, can effectively improve the system performance of TDS-OFDM systems. The correlation of two successive preambles is employed to estimate the average noise power as the threshold for obtaining the SCTD threshold estimation error and loss path information in large delay spread channel environments. The proposed estimation scheme roughly predicts the noise power in order to choose the significant channel taps to estimate the channel impulse response. Some comparative simulations are given to show that the proposed technique has the potential to achieve bit error rate performance superior to that of the conventional least squares channel estimation.

As one of the promising techniques in Broadband Wireless Access (BWA), IEEE 802.16 also namely WiMax provides wide-area, high-speed, and non-line-of-sight wireless transmission to support multimedia services. Four service types are defined in the specification of IEEE 802.16 for QoS support. In order to achieve end-to-end multimedia services, 802.16 QoS must be well integrated with IP QoS. In this paper, we propose a framework of cross-layer QoS support in the IEEE 802.16 network. Two novel mechanisms are proposed in the framework for performance improvement: Fragment Control and Remapping. Fragment Control handles the data frames that belong to the same IP datagram in an atomic manner to reduce useless transmission. Remapping is concerned with the mapping rules from IP QoS to 802.16 QoS and is designed to reduce the impact of traffic burstiness on buffer management. Simulation study has shown that the proposed scheme has higher goodput and throughput, and lower delay than the contrast.

This paper addresses the sensing-throughput tradeoff problem by using cluster-based cooperative spectrum sensing (CSS) schemes in two-layer hierarchical cognitive radio networks (CRNs) with soft data fusion. The problem is formulated as a combinatorial optimization problem involving both discrete and continuous variables. To simplify the solution, a reasonable weight fusion rule (WFR) is first optimized. Thus, the problem devolves into a constrained discrete optimization problem. In order to efficiently and effectively resolve this problem, a lexicographical approach is presented that solving two optimal subproblems consecutively. Moreover, for the first optimal subproblem, a closed-form solution is deduced, and an optimal clustering scheme (CS) is also presented for the second optimal subproblem. Numerical results show that the proposed approach achieves a satisfying performance and low complexity.

This paper presents a hybrid architecture for a neural network (NN) trained by a particle swarm optimization (PSO) algorithm. The NN is implemented on the hardware side while the PSO is executed by a processor on the software side. In addition, principal component analysis (PCA) is also applied to reduce correlated information. The PCA module is implemented in hardware by the SystemVerilog programming language to increase operating speed. Experimental results showed that the proposed architecture had been successfully implemented. In addition, the hardware-based NN trained by PSO (NN-PSO) program was faster than the software-based NN trained by the PSO program. The proposed NN-PSO with PCA also obtained better recognition rates than the NN-PSO without-PCA.

This work explores generative models of handwritten digit images using natural elastic nets. The analysis aims to extract global features as well as distributed local features of handwritten digits. These features are expected to form a basis that is significant for discriminant analysis of handwritten digits and related analysis of character images or natural images.

The Euclidean projection operation is the most complex and time-consuming of the alternating direction method of multipliers (ADMM) decoding algorithms, resulting in a large number of resources when deployed on hardware platforms. We propose a simplified line segment projection algorithm (SLSA) and present the hardware design and the quantization scheme of the SLSA. In simulation results, the proposed SLSA module has a better performance than the original algorithm with the same fixed bitwidths due to the centrosymmetric structure of SLSA. Furthermore, the proposed SLSA module with a simpler structure without hypercube projection can reduce time consuming by up to 72.2% and reduce hardware resource usage by more than 87% compared to other Euclidean projection modules in the experiments.

Linear programming (LP) decoding based on the alternating direction method of multipliers (ADMM) has proved to be effective for low-density parity-check (LDPC) codes. However, for high-density parity-check (HDPC) codes, the ADMM-LP decoder encounters two problems, namely a high-density check matrix in HDPC codes and a great number of pseudocodewords in HDPC codes' fundamental polytope. The former problem makes the check polytope projection extremely complex, and the latter one leads to poor frame error rates (FER) performance. To address these issues, we introduce the even vertex algorithm (EVA) into the ADMM-LP decoding algorithm for HDPC codes, named as HDPC-EVA. HDPC-EVA can reduce the complexity of the projection process and improve the FER performance. We further enhance the proposed decoder by the automorphism groups of codes, creating diversity in the parity-check matrix. The simulation results show that the proposed decoder is capable of cutting down the average decoding time for each iteration by 30%-60%, as well as achieving near maximum likelihood (ML) performance on some BCH codes.

To simultaneously support guaranteed real-time services and best-effort service, a Priority-based Scheduling Architecture (PSA) designed for high-speed switches is proposed. PSA divides packet scheduling into high-priority phase and low-priority phase. In the high-priority phase, an improved sorted-priority algorithm is presented. It introduces a new constraint into the scheduling discipline to overcome bandwidth preemption. Meanwhile, the virtual time function with a control factor α is employed. Both computer simulation results and theoretic analysis show that the PSA mechanism has excellent performance in terms of the implementation complexity, fairness and delay properties.

In this paper, we present CB-Power, a hierarchical power analysis and characterization environment of cell-based CMOS circuits. The environment includes two parts, a cell characterization system for timing, input capacitance as well as power and a cell-based power estimation system. The characterization system can characterize basic, complex and transmission gates. During the characterization, input slew rate, output loading, capacitive feedthrough effect and the logic state dependence of nodes in a cell are all taken into account. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power and dynamic power. With the characterization data, a cell-based power estimator (CBPE) embedded in Verilog-XL is used for estimating the power consumption of the gates in a circuit. CBPE is also a hierarchical power estimator. Macrocells such as flip-flops and adders are partitioned into primitive gates during power estimation. Experimental results on a set of MCNC benchmark circuits show that the power estimation based on our power modeling and characterization provides within 6% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.

As the function of a system getting more complex, IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of their IP blocks a secret. An IP level power model is a model that takes only the primary input statistics as parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method for power models based on power sensitivities. By analyzing the relationship between the dynamic power consumption of CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis, the first nominal point is selected to minimize the average estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can be applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby, it is a promising method for IP level power model construction.

Multiple access interferecnce (MAI) is a major factor limiting the performance of direct-sequence code-division multiple access (DS-CDMA) systems. Since the amount of MAI is dependent on the correlation among user signals, one way to reduce it is to reduce such correlation. In mobile multiuser communication, each user experiences a different time-varying channel response. This user-dependent characteristic in channel variation can be exploited to assist the separation of different user signals, in addition to the capability provided by the spreading codes. As the correlation among different user channels are expected to decrease with increase in time span, enhanced decorrelation among different users' signals can be effected by spacing out the chips of one modulated symbol in time. Thus we consider chip-interleaving DS-CDMA (CI-DS-CDMA) in this study. We investigate its performance through theoretical analysis and computer simulation. Employing only a slightly modified rake receiver structure, CI-DS-CDMA is shown to attain significant performance gain over conventional DS-CDMA, in multiple access communication over single- and multi-path fading channels, without complicated multiuser detection. CI-DS-CDMA also has a lower demand for short-term power control than conventional DS-CDMA, especially in one-path Rayleigh fading. Results of the theoretical analysis and the computer simulation agree well with each other.

The electrical properties of poly-Si thin film transistors (TFTs) using rapid thermal annealing with various gate oxide thicknesses were studied in this work. It was found that Poly-Si TFT electrical characteristics with the thinnest gate oxide thickness after RTA treatment exhibits the largest performance improvement compared to TFT with thick oxide as a result of the increased incorporated amounts of the nitrogen and oxygen. Thus, the combined effects can maintain the advantages and avoid the disadvantages of scaled-down oxide, which is suitable for small-to-medium display mass production.