In this paper, we propose a register file with data bypassing function. This register file bypasses data using data bypassing units instead of functional units when actual operation in functional units such as ALU is unnecessary. Applying this method to a general purpose microprocessor with benchmark programs, we demonstrate 50% power consumption reduction in functional units. Though length of bus lines increases a little due to an additional hardware in register file, as buses are not driven when data is bypassed, power consumption in bus lines is also reduced by 40% compared with the conventional architecture.

This paper proposes a time-to-digital converter (TDC) utilizing the cascaded time difference amplifier (TDA) and shows measurement results with 0.18 µm CMOS. The proposed TDC operates in two modes, a wide input range mode and a fine time resolution mode. We employ a non-linearity calibration technique based on a lookup table. The wide input range mode shows 10.2 ps time resolution over 1.3 ns input range with DNL and INL of +0.8/-0.7LSB and +0.8/-0.4LSB, respectively. The fine time resolution mode shows 1.0 ps time resolution over 60 ps input range with DNL and INL of +0.9/-0.9LSB and +0.8/-1.0LSB, respectively.

This paper demonstrates an autonomous di/dt control of power supply for margin aware operation. A di/dt on the power line is detected by a mutual inductor, the induced voltage is multiplied by Gilbert multiplier and the following low pass filter outputs a DC voltage in proportion to the di/dt. The DC voltage is compared with reference voltages, and the modes of the internal circuit is controlled depending on the comparators output. By using this scheme, the di/dt noise power can be autonomously controlled to fall within a defined range set by the reference voltages. Our experimental results show that the internal circuit oscillates between the all-active and the half-active modes, also show that the all/half ratio and the oscillation frequency changes depending on the reference voltages. It proves that our autonomous di/dt noise control scheme works as being designed.

In this paper, we present a pixel-level color image sensor with efficient ambient light suppression using a modulated RGB flashlight to support a recognition system. The image sensor employs bidirectional photocurrent integrators for pixel-level demodulation and ambient light suppression. It demodulates a projected flashlight with suppression of an ambient light at short intervals during an exposure period. In the imaging system using an RGB modulated flashlight, every pixel provides innate color and depth information of a target object for color-based categorization and depth-key object extraction. We have designed and fabricated a prototype chip with 6464 pixels using a 0.35 µm CMOS process. Color image reconstruction and time-of-flight range finding have been performed for the feasibility test.

The Internet of Things (IoT) implicates an infrastructure that creates new value by connecting everything with communication networks, and its construction is rapidly progressing in anticipation of its great potential. Enhancing the security of IoT is an essential requirement for supporting IoT. For ensuring IoT security, it is desirable to create a situation that even a terminal component device with many restrictions in computing power and energy capacity can easily verify other devices and data and communicate securely by the use of public key cryptography. To concretely achieve the big goal of penetrating public key cryptographic technology to most IoT end devices, we elaborated the secure cryptographic unit (SCU) built in a low-end microcontroller chip. The SCU comprises a hardware cryptographic engine and a built-in access controlling functionality consisting of a software gate and hardware gate. This paper describes the outline of our SCU construction technology's research and development and prospects.

This paper presents a new high-speed and area-efficient dual-rail PLA. The proposed circuit includes three schemes: 1) a divided column scheme (DCS), 2) a programmable sense-amplifier activation scheme (PSAS), and 3) an interdigitated column scheme (ICS). In the DCS, a column circuit of a PLA is divided and each circuit operates in parallel. This enhances the performance of the PLA, and this scheme becomes more effective as input data bandwidth increases. The PSAS is used to generate an activation pulse for sense amplifiers in the PLA. In this scheme, the proposed delay generators enable to minimize a timing margin depending on process variations and operating conditions. The ICS is used to enhance the area-efficiency of the PLA, where a method of physical compaction is employed. This scheme is effective for circuits which have the regularity in logic function such as arithmetic circuits. As applications of the proposed PLA, a comparator, a priority encoder, and an incrementor for 128-bit data processing were designed. The proposed circuit design schemes achieved a 22.2% delay reduction and a 37.5% area reduction on average over the conventional high-speed and low-power PLA in a 0.13-µm CMOS technology with a supply voltage of 1.2 V.

In this paper, a high-speed PLA based on dynamic array logic circuits with latch sense amplifiers is presented. The present circuit consists of logic cell arrays, dual-rail bit-lines, latch sense amplifiers, and control blocks. By using a charge sharing scheme and latch sense amplifiers, voltage swings of the bit-lines are reduced compared to the conventional circuits, thus a high-speed and low-power operation is achieved. The present array logic configuration can realize any logic function expressed in the sum-of-products form by using PLA structure. As an application of the proposed PLA, a 32-bit binary comparator is designed and implemented in a 0.6-µm double-poly triple-metal CMOS process. Results of HSPICE simulation show a better performance compared to the conventional circuits. Functional testing using electron beam probing shows that the present circuit operates correctly.

This paper proposes a deep neural network named BayesianPUFNet that can achieve high prediction accuracy even with few challenge-response pairs (CRPs) available for training. Generally, modeling attacks are a vulnerability that could compromise the authenticity of physically unclonable functions (PUFs); thus, various machine learning methods including deep neural networks have been proposed to assess the vulnerability of PUFs. However, conventional modeling attacks have not considered the cost of CRP collection and analyzed attacks based on the assumption that sufficient CRPs were available for training; therefore, previous studies may have underestimated the vulnerability of PUFs. Herein, we show that the application of Bayesian deep neural networks that incorporate Bayesian statistics can provide accurate response prediction even in situations where sufficient CRPs are not available for learning. Numerical experiments show that the proposed model uses only half the CRP to achieve the same response prediction as that of the conventional methods. Our code is openly available on https://github.com/bayesian-puf-net/bayesian-puf-net.git.

BLS signature is an elliptic curve cryptography with an attractive feature that signatures can be aggregated and shortened. We have designed two ASIC architectures for hashing to the elliptic curve and pairing to minimize the latency. Also, the designs are optimized for BLS12-381, a relatively new and safe curve.

We have realized a design automation platform of hardware accelerator for pairing operation over multiple elliptic curve parameters. Pairing operation is one of the fundamental operations to realize functional encryption. However, known as a computational complexity-heavy algorithm. Also because there have been not yet identified standard parameters, we need to choose curve parameters based on the required security level and affordable hardware resources. To explore this design optimization for each curve parameter is essential. In this research, we have realized an automated design platform for pairing hardware for such purposes. Optimization results show almost equivalent to those prior-art designs by hand.

In this work, template attacks that aimed to leak the nonce were performed on 256-bit ECDSA hardware to evaluate the resistance against side-channel attacks. The target hardware was an ASIC and was revealed to be vulnerable to the combination of template attacks and lattice attacks. Furthermore, the attack result indicated it was not enough to fix the MSB of the nonce to 1 which is a common countermeasure. Also, the success rate of template attacks was estimated by simulation. This estimation does not require actual hardware and enables us to test the security of the implementation in the design phase. To clarify the acceptable amount of the nonce leakage, the computational cost of lattice attacks was compared to that of ρ method which is a cryptanalysis method. As a result, the success rate of 2-bit leakage of the nonce must be under 62% in the case of 256-bit ECDSA. In other words, SNR must be under 2-4 in our simulation model.

This paper proposes a cell layout synthesis technique to minimize the sensitivity to wiring faults due to spot defects. We modeled the sensitivity to faults on intra-cell routings with consideration to the spot defects size distribution and the end effect of critical areas. The effect of the sensitivity reduction on the yield is also discussed. By using the model as a cost function, we comprehensively generate the minimum width layout of CMOS logic cells and select the optimal layouts. Experimental results show that our technique reduces about 15% of the fault sensitivities compared with the wire-length-minimum layouts for benchmark CMOS logic circuits which have up to 14 transistors.

In modern CMOS digital design, the noise immunity has come to have an almost equal importance to the power consumption. In the last decade, many low power design schemes have been presented. However, no one can simply judge which one is the best from the noise immunity point of view. In this paper, we investigate the noise immunity of the static CMOS low power design schemes in terms of logic and delay errors caused by different kinds of noise existing in the static CMOS digital circuits. To fulfill the aims of the paper, first a model representing the different sources of noise in deep submicron design is presented. Then the model is applied to the most famous low power design schemes to find out the most robust one with regard to noise. Our results show the advantages of the dual threshold voltage scheme over other schemes from the noise immunity point of view. Moreover, it indicates that noise should be carefully taken into account when designing low power circuits; otherwise circuit performance would be unexpected. The study is carried out on three circuits; each is designed in five different schemes. The analysis is done using HSPICE, assuming 0.18 µm CMOS technology.

This paper proposes flat and hierarchical approaches for generating a minimum-width transistor placement of CMOS cells in presence of non-dual P and N type transistors. Our approaches are the first exact method which can be applied to CMOS cells with any types of structure. Non-dual CMOS cells occupy a major part of an industrial standard-cell library. To generate the exact minimum-width transistor placement of non-dual CMOS cells, we formulate the transistor placement problem into Boolean Satisfiability (SAT) problem considering the P and N type transistors individually. Using the proposed method, the transistor placement problem of any types of CMOS cells can be solved exactly. In addition, the experimental results show that our flat approach generates smaller width placement for 29 out of 103 dual cells than that of the conventional method. Our hierarchical approach reduces the runtimes drastically. Although this approach has possibility to generate wider placements than that of the flat approach, the experimental results show that the width of only 3 out of 147 cells solved by our hierarchical approach are larger than that of the flat approach.