ZigBee recently has been used a lot in wireless sensor networks because of its low power consumption and affordable chips. However, ZigBee's existing hierarchical routing algorithm has a disadvantage in that a node may communicate with a nearby node over several hops. In this letter we propose a Quasi-Hierarchical Routing (QHR) algorithm that can improve the ZigBee hierarchical routing method's inefficiency by using brief information on neighbors within radio range. The network simulation evaluates this QHR's performance by comparing it to other ZigBee routing schemes.

In this paper, we propose a novel target acoustic signal detection approach which is based on non-negative matrix factorization (NMF). Target basis vectors are trained from the target signal database through NMF, and input vectors are projected onto the subspace spanned by these target basis vectors. By analyzing the distribution of time-varying normalized projection error, the optimal threshold can be calculated to detect the target signal intervals during the entire input signal. Experimental results show that the proposed algorithm can detect the target signal successfully under various signal environments.

An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13 µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100 ns TLP system. From the HBM/ CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1 kV, MM 100 V and CDM 500 V.

Most digital signal processing (DSP) algorithms for multimedia and communication applications require multiplication and addition operations. Especially matrix-matrix or matrix-vector the multiplications frequently used in DSP implementations needs inner product arithmetic which takes the most processing time. Also multiplications for the DSP algorithms for software defined radio (SDR) applications require different input bitwidths. Therefore, the multiplications for inner product need to be sufficiently flexible in terms of bitwidths to utilize hardware resources efficiently. This paper proposes a novel reconfigurable inner product architecture based on a pipelined adder array, which offers increased flexibility in bitwidths of input arrays. The proposed architecture consists of sixteen 44 multipliers and a pipelined adder array and can compute the inner product of input arrays with any combination of multiples of 4 bitwidths such as 44, 48, 412, ... 1616. Experimental results show that the proposed architecture has latency of maximum 9 clock cycles and throughput of 1 clock cycle for inner product of various bitwidths of input arrays. When TSMC 0.18 µm libraries are used, the chip area and critical path of the proposed architecture are 186,411 gates and 2.79 ns, respectively. The proposed architecture can be applied to a reconfigurable arithmetic engine for real-time SDR system designs.

In live multimedia applications with multiple videos, it is necessary to develop an efficient mechanism of multiplexing several MPEG video streams into a single stream and transmitting it over network without wasting excessive bandwidth. In this paper, we present an efficient multiplexing and traffic smoothing scheme for multiple variable bit rate (VBR) MPEG video streams in live video applications with finite buffer sizes. First, we describe the constraints imposed by the allowable delay bound for each elementary stream and by the multiplexer/receiver buffer sizes. Based on these constraints, a new multiplexing and traffic smoothing scheme is designed in such a way as to smooth maximally the multiplexed transmission rate by exploiting temporal and spatial averaging effects, while avoiding the buffer overflow and underflow. Through computer experiments based on an MPEG-coded video trace of Star-wars, it is shown that the proposed scheme significantly reduces the peak rate, coefficient of variation, and effective bandwidth of the multiplexed transmission rate.

We propose two multipriority reservation protocols for wavelength division multiplexing (WDM) networks. The network architecture is a single-hop with control channel-based passive star topology. Each station is equipped with two pairs of laser and filter. One pair of laser and filter is always tuned to wavelength λ0 for control and the other pair of laser and filter can be tuned to any of data wavelengths, λ1, λ2, ..., λN. According to the access methods of the control channel, one protocol is called slotted ALOHA-based protocol and the other protocol is called TDM-based protocol. The two protocols have the following properties. First, each of them has its own priority control scheme which easily accommodates multipriority traffics. Second, they can be employed in the network with limited channels, i.e. the number of stations in the system is not restricted by the number of data channels. Third, they are conflict-free protocols. By using a reservation scheme and a distributed arbitration algorithm, channel collision and destination conflict can be avoided. For the performance point of view, the TDM-based protocol gives an optimal solution for the priority control. However it is less scalable than the slotted ALOHA-based protocol. The slotted ALOHA-based protocol also performs good priority control even though it is not an optimal solution. We analyze their performances using a discrete time Markov model and verify the results by simulation.

We propose a new broadcast strategy for a multiple-input multiple-output (MIMO) system with N transmit antennas at the transmitter and M≤N single antenna receivers. The proposed method, based on dirty-paper coding (DPC), spatially separates the M users but does not suffer from the power loss of classical spatial division multiple access (SDMA). For the special case of M=N=2 and when the two single antenna receivers are assumed to be co-located, the proposed scheme produces a 2 transmit, 2 receiver antenna MIMO transmission system that doubles the symbol rate of MIMO space-time block code (STBC) systems from one to two symbol per transmission time. It is proved theoretically and experimentally that the proposed scheme provides the same performance level as that of MIMO STBC systems (i.e., the Alamouti scheme) for the first symbol, and the same performance as the Bell labs layered space-time (BLAST) system for the second symbol. When compared to the BLAST system, the proposed scheme has the same symbol rate, but achieves significantly better performance, since it provides 2 level diversity per symbol on the first symbol while the BLAST system does not provide any diversity.

This paper presents a novel low-cost high-performance CAVLC decoder for H.264/AVC. The proposed CAVLC decoder generates the length of coeff_token and total_zeros symbols with simple arithmetic operation. So, it can be implemented with reduced look-up table. And we propose multi-symbol run_before decoder which has enhanced throughput. It can decode more than 2.5 symbols in a cycle if there are run_before symbols to be decoded. The hardware cost is about 12 K gates when synthesized at 125 MHz.

For analog applications, the Metal-Insulator-Metal (MIM) capacitance has to be measured at a much higher resolution than using the conventional methods, i.e. to a sub-femto level. A new robust mismatch measurement technique is proposed, which is more accurate and robust compared to the conventional Floating Gate Capacitance Measurement (FGCM) methods. A capacitance mismatching measurement methodology based on Vs is more stable than that based on Vf because the influence of pre-existing charge in the floating-gate can be cancelled in the slope of ΔVs/ΔVf based on Vs. The accuracy of this method is evaluated through silicon measurement in a 0.13 µm technology. It shows that, compared to the ideal value, the average of the new method are within 0.12% compared to 49.23% in conventional method while the standard deviation is within 0.15%.

The IEEE 802.16j mobile multi-hop relay (MMR) is studied to improve throughput, extend coverage, and increase capacity. Mobile relay stations attached to vehicles make arbitrary movements and have interference with other base stations or relay stations, thus lowering service functions. This study sets out to suggest an interference detection and avoidance method and evaluates its performance in order to help introduce a mobile relay station for vehicle mounting in a mobile multi-hop relay network. The proposed approach would be implemented by the addition of MAC management messages at a base or relay station instead of the change of mobile station.

For the High Efficiency Video Coding (HEVC) standard, a fast transform unit (TU) decision method is proposed. HEVC defines the TU representing a region sharing the same transformation, and it supports various transform sizes from 4×4 to 32×32 by using a quadtree of TUs. The various sizes of TUs can provide good coding efficiency, whereas it may dramatically increase encoding complexity. Assuming that a TU with highly compacted energy is unlikely to be split, the proposed method determines an appropriate TU size according to the position of the last non-zero transform coefficient. Experimental results show that this reduces encoding run time by 17.2% with a negligible coding loss of 0.78% BD-rate for the random-access scenario.

Advances in ILP techniques enable strict consistency models to relax memory order through speculative execution of memory operations. However, ordering constraints still hinder the performance because speculatively executed operations cannot be committed out of program order for the possibility of mis-speculation. In this paper, we propose a new technique which allows memory operations to be non-speculatively committed out of order without violating consistency constraints. Consistency constraints are guaranteed through delaying the coherence requests. The proposed technique also improves the performance of spin lock primitives such as TTS lock or MCS lock. Through delaying early acquire requests, the lock transfer time can be improved when there is high contention for a lock.

This paper presents a novel algorithm which generates a beam pattern having maximum gain towards target direction. The new technique utilizes a Generalized Conjugate Gradient Method (CGM) based on the conventional CGM for obtaining the optimal weight vector. The proposed method finds a weight vector that maximizes the SINR (Signal to Interference plus Noise Ratio). Based on the an analysis of the results of various computer simulations, it is observed that the proposed algorithm is suitable for the IS2000 1X mobile communication environments.

This paper introduces a new folding amplifier in a folding and interpolating 10-b ADC. The amplifier consists of current mirrors and differential stages. Only one current source is exploited in cascaded differential pairs, which reduces the power consumption significantly. In the folding circuit, the interpolation is implemented with a current division technique. An experiment of the amplifier in 10-b folding signal has been integrated in a single-poly four-metal 0.35 µm CMOS process. The simulation in 10-b folding ADC shows that power consumption is 225 mW at the sampling speed of 250 Msample/s and the power supply of 3.3 V. The preliminary experiment indicates the current steering folder and digital bits operate as expected.

In this paper, we propose multicast technique in order to reduce the required network bandwidth by n times, by merging the adjacent multicasts depending on the number of HENs (Head-End-Nodes) n that request the same video. Allowing new clients to immediately join an existing multicast through patching improves the efficiency of the multicast and offers services without any initial latency. A client might have to download data through two channels simultaneously, one for multicast and the other for patching. Each video stream is divided into blocks which are the same size of multicast grouping interval Im. Blocks then are evenly distributed into different HENs according to their popularity and the order of requests. Only when the playback time exceeds the amount of cached video data, server generates new multicast channel. Since the interval of multicast can be dynamically expanded according to the popularity of videos, it can be reduced the server's workload and the network bandwidth. We adopt the cache replacement strategy as LFU (Least-Frequently-Used) for popular videos, LRU (Least-Recently-Used) for unpopular videos, and the method for replacing the first block of video last to reduce end-to-end latency. We perform simulations to compare its performance with that of conventional multicast. From simulation results, we confirm that the proposed multicast technique offers substantially better performance.

Threshold Inverter Quantization (TIQ) technique has been gaining its importance in high speed flash A/D converters due to its fast data conversion speed. It eliminates the need of resistor ladders for reference voltages generation which requires substantial power consumption. The key to TIQ comparators design is to generate 2n - 1 different sized TIQ comparators for an n-bit A/D converter. This paper presents a highly efficient TIQ comparator design methodology based on an analytical model as well as SPICE simulation experimental model. One can find any sets of TIQ comparators efficiently using the proposed method. A 6-bit TIQ A/D converter has been designed in a 0.18 µm standard CMOS technology using the proposed method, and compared to the previous measured results in order to verify the proposed methodology.

The performance of an orthogonal frequency division multiplexing (OFDM) system is degraded if the peak-to-average power ratio (PAPR) is high. In general, in order to obtain optimal PAPR reduction using the partial transmitted sequence (PTS) technique, an exhaustive search of the possible subblocks and rotation factors must be done. As the number of subblocks and rotation factors increases, PAPR reduction improves, but the computational load becomes impractical. In order to reduce the complexity while still improving the OFDM system performance, a new method using a genetic algorithm (GA) is proposed to find a set of rotation factors that reduces both the PAPR and the computational load. A comparison is made between the proposed method and previously developed techniques such as exhaustive and gradient descent PTS methods. The superiority of the proposed method is demonstrated as a reduction in computational load compared with exhaustive PTS and the gradient method, and an improvement in performance compared with the iterative and gradient methods.

This paper presents a coexistence model of IEEE 802.15.4 with IEEE 802.11b interference in fading channels and proposes two adaptive channel allocation schemes. The first avoids the IEEE 802.15.4 interference only and the second avoids both of the IEEE 802.15.4 and IEEE 802.11b interferences. Numerical results show that the proposed algorithms are effective for avoiding interferences and for maximizing network capacity since they select a channel which gives the maximum signal to noise ratio to the system.

In this paper, we present and verify a new chip-package co-modeling and simulation approach for a low-noise chip-package hierarchical power distribution network (PDN) design. It is based on a hierarchical modeling to combine distributed circuit models at both chip-level PDN and package-level PDN. In particular, it includes all on- and off-chip parasitic circuit elements in the hierarchical PDN with a special consideration on on-chip decoupling capacitor design and placement inside chip. The proposed hierarchical PDN model was successfully validated with good correlations and subsequent analysis to a series of Z11 and Z21 PDN impedance measurements with a frequency range from 1 MHz to 3 GHz. Using the proposed model, we can analyze and estimate the performance of the chip-package hierarchical PDN as well as can predict the effect of high frequency electromagnetic interactions between the chip-level PDN and the package-level PDN. Furthermore, we can precisely anticipate PDN resonance frequencies, noise generation sources, and noise propagation paths through the multiple levels in the hierarchical PDN.

We propose a query language based on extended regular expressions. This language extends texts with text-generating macros. These macros make it possible to define languages in a compressed, elegant way. This paper also extends queries with linear implications and additive (classical) conjunctions. To be precise, it allows goals of the form D —ο G and G1&G2 where D is a text or a macro and G is a query. The first goal is solved by adding D to the current text and then solving G. This goal is flexible in controlling the current text dynamically. The second goal is solved by solving both G1 and G2 from the current text. This goal is particularly useful for internet search.