To control various access privileges in group-oriented applications having multiple data streams, we present a novel reactive key management scheme where each member can obtain the key of a data stream from public parameters only when necessary. Compared with the previous schemes, this scheme significantly reduces the amount of rekey messages for dynamic membership change due to its reactive nature.

Cache performance optimization is an important design consideration in building high-performance embedded processors. Unlike general-purpose microprocessors, embedded processors can take advantages of application-specific information in optimizing the cache performance. One of such examples is to use modified cache index bits (over conventional index bits) based on memory access traces from key target embedded applications so that the number of conflict misses can be reduced. In this paper, we present a novel fine-grained cache reconfiguration technique which allows an intra-program reconfiguration of cache index bits, thus better reflecting the changing characteristics of a program execution. The proposed technique, called dynamic reconfiguration of index bits (DRIB), dynamically changes cache index bits in the function level. This compiler-directed and fine-grained approach allows each function to be executed using its own optimal index bits with no additional hardware support. In order to avoid potential performance degradation by frequent cache invalidations from reconfiguring cache index bits, we describe an efficient algorithm for selecting target functions whose cache index bits are reconfigured. Our algorithm ensures that the number of cache misses reduced by DRIB outnumbers the number of cache misses increased from cache invalidations. We also propose a new cache architecture, Two-Level Indexing (TLI) cache, which further reduces the number of conflict misses by intelligently dividing indexing steps into two stages. Our experimental results show that the DRIP approach combined with the TLI cache reduces the number of cache misses by 35% over the conventional cache indexing technique.

In this paper, we propose CRadix sort, a new string sorting algorithm based on MSD radix sort. CRadix sort causes fewer cache misses than MSD radix sort by uniquely associating a small block of main memory called the key buffer to each key and temporarily storing a portion of each key into its corresponding key buffer. Experimental results in running time comparisons with other string sorting algorithms are provided for showing the effectiveness of CRadix sort.

The extended version of spectral domain approach (ESDA) is applied to evaluate the scattering characteristics of discontinuities in coaxial line. Discontinuities may be in inner and/or outer conductor of coaxial line. This method secures the high accuracy by considering the singularities of fields near the conductor edge properly. The computational labor of the new method is far lighter than that of FEM, so that novel method is suitable for the time consuming iterative computation such as fitting procedure in material evaluation or optimization of antenna design.

A ridge-type Zn-indiffused Mach-Zehnder modulator operating at 1.55 µm wavelength is demonstrated on a z-cut LiNbO3 substrate for the first time. The measured results show that the values of voltage-length product can be reduced from 9.6 V-cm to 8.1 V-cm with the etched depth of 1.7 µm.

Providing data availability in a high performance computing environment is very important, especially in this data-intensive world. Most clusters either equip with RAID (Redundant Array of Independent Disks) devices or use redundant nodes to protect data from loss. However, neither of these can really solve the reliability problem incurred in a striped file system. Striping provides an efficient way to increase I/O throughput both in the distributed and parallel paradigms. But it also reduces the overall reliability of a disk system by N fold, where N is the number of independent disks in the system. Parallel Virtual File System (PVFS) is an open source parallel file system which has been widely used in the Linux environment. Its striping structure is good for performance but provides no fault tolerance. We implement Reliable Parallel File System (RPFS) based on PVFS but with reliability support. Our quantitative analysis shows that MTTF (Mean Time To Failure) of our RPFS is better than that of PVFS. Besides, we propose a parity cache table (PCT) to alleviate the penalty of parity updating. The evaluation of our RPFS shows that its read performance is almost the same as that of PVFS (2% to 13% degradation). As to the write performance, 28% to 45% improvement can be achieved depending on the behavior of the operations.

In this paper, we propose a method of accelerating test generation for sequential circuits by using the knowledge about the availability of state justification sequences, the bound on the length of state distinguishing sequences, differentiation between valid and invalid states, and the existence of a reset state. We also propose a method of synthesis for testability (SfT) which takes the features of our test generation method into consideration to synthesize sequential circuits from given FSM descriptions. The SfT method guarantees that the test generator will be able to find a state distinguishing sequence. The proposed method extracts the state justification sequence from the FSM produced by the synthesizer to improve the performance of its test generation process. Experimental results show that the proposed method can achieve 100% fault efficiency in relatively short test generation time.

While web proxy caching is a widely deployed technique, the performance of a proxy cache is limited by the local storage. Some studies have addressed this limitation by using the residual resources of clients via a p2p method and have achieved a very high hit rate. However, these approaches treat web objects as homogeneous objects and there is no consideration of various web characteristics. Consequently, the byte hit rate of the system is limited, external bandwidth is wasted, and perceived user latency is increased. The present paper suggests an efficient p2p based web caching technique that manages objects with different policies so as to exploit the characteristics of web objects, such as size and temporal locality. Small objects are stored alone whereas large objects are stored by dividing them into numerous small blocks, which are distributed in clients. On a proxy cache, header blocks of large objects take the place of objects themselves and smaller objects are cached. This technique increases the hit rate. Unlike a web cache, which evicts large objects as soon as possible in the case where clients fulfill the role of backup storage, large objects are given higher priority than small objects in the proposed approach. This maximizes the effect of hits for large objects and thereby increases the byte hit rate. Furthermore, we construct simple latency models for various p2p based web caching systems and analyze the effects of the proposed policies on these systems. We then examine the performances of the efficient policies via a trace driven simulation. The results demonstrate that the proposed techniques effectively enhance web cache performance, including hit rate, byte hit rate, and response time.

A historical overview of microoptomechatronics technologies is presented for positioning of microoptomechatronics, accompanied with a future view based on the current state of art nanotechnologies. How the technologies have been developed for realizing practical precision and information devices based on optics or photonics is also mentioned, citing a few examples.

The present paper proposes a novel cache architecture, called SCache, to detect buffer overflow attacks at run time. In addition, we evaluate the energy-security efficiency of the proposed architecture. On a return-address store, SCache generates one or more copies of the return address value and saves them as read only in the cache area. The number of copies generated strongly affects both energy consumption and vulnerability. When the return address is loaded (or popped), the cache compares the value loaded from the memory stack with the corresponding copy existing in the cache. If they are not the same, then return-address corruption has occurred. In the present study, the proposed approach is shown to protect more than 99.5% of return-address loads from the threat of buffer overflow attacks, while increasing the total cache-energy consumption by, at worst, approximately 23%, compared to a well-known low-power cache. Furthermore, we explore the tradeoff between energy consumption and security, and our experimental results show that an energy-aware SCache model provides relatively higher security with only a 10% increase in energy consumption.

Technical terms are linguistic representations of a domain concept, and their constituents are components used to represent the concept. Technical terms are usually multi-word terms and their meanings can be inferred from their constituents. Therefore, term constituents are essential for understanding the designated meaning of technical terms. However, there are several problems in finding the correct meanings of technical terms with their term constituents. First, because a term constituent is usually a morphological unit rather than a conceptual unit in the case of Korean technical terms, we need to first identify conceptual units by chunking term constituents. Second, conceptual units are sometimes homonyms or synonyms. Moreover their meanings show domain dependency. It is therefore necessary to give information about conceptual units and their possible meanings, including homonyms, synonyms, and domain dependency, so that natural language applications can properly handle technical terms. In this paper, we propose a term constituent alignment algorithm that extracts such information from bilingual technical term pairs. Our algorithm recognizes conceptual units and their meanings by finding English term constituents and their corresponding Korean term constituents for given English-Korean term pairs. Our experimental results indicate that this method can effectively find conceptual units and their meanings with about 6% alignment error rate (AER) on manually analyzed experimental data and about 14% AER on automatically analyzed experimental data.

The output limits of the power system stabilizer (PSS) can improve the system damping performance immediately following a large disturbance. Due to non-smooth nonlinearities from the saturation limits, these values cannot be determined by the conventional tuning methods based on linear analysis. Only ad hoc tuning procedures have been used. A nonlinear least squares method, which is the Gauss-Newton optimization algorithm, is used in this paper. The gradient required in the Gauss-Newton method can be computed by applying trajectory sensitivities from the hybrid system model with the differential-algebraic-impulsive-switched (DAIS) structure. The optimal output limits of the PSS tuned by the proposed method are evaluated by time-domain simulation in a multi-machine power system (MMPS).

Most commercial Web sites dynamically generate their contents through a three-tier server architecture composed of a Web server, an application server, and a database server. In such an architecture, the database server easily becomes a bottleneck to the overall performance. In this paper, we propose WDBAccel, a high-performance database server accelerator that significantly improves the throughput of database processing. WDBAccel eliminates costly, complex query processing needed to obtain query results by reusing the results from previous queries for subsequent queries. This differentiates WDBAccel from other database cache systems, which employ traditional query processing. WDBAccel further improves its performance by fully utilizing main memory as the primary storage. This paper presents the design and implementation of the WDBAccel as well as the results of performance evaluation with a prototype.

A novel cache-based network processor (NP) architecture that can catch up with next generation 100-Gbps packet-processing throughput by exploiting a nature of network traffic is proposed, and the prototype is evaluated with real network traffic traces. This architecture consists of several small processing units (PUs) and a bit-stream manipulation hardware called a burst-stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC) and a cache-miss handler (CMH). The PLC memorizes a packet-processing method with all table-lookup results, and applies it to subsequent packets that have the same information in their header. To avoid packet-processing blocking, the CMH handles cache-miss packets while registration processing is performed at the PLC. The combination of the PLC and CMH enables most packets to skip the execution at the PUs, which dissipate huge power in conventional NPs. We evaluated an FPGA-based prototype with real core network traffic traces of a WIDE backbone router. From the experimental results, we observed a special case where the packet of minimum size appeared in large quantities, and the cache-based NP was able to achieve 100% throughput with only the 10%-throughput PUs due to the existence of very high temporal locality of network traffic. From the whole results, the cache-based NP would be able to achieve 100-Gbps throughput by using 10- to 40-Gbps throughput PUs. The power consumption of the cache-based NP, which consists of 40-Gbps throughput PUs, is estimated to be only 44.7% that of a conventional NP.

A highly collision-resistive RFID system multiplexes communications between thousands of transponders and a single reader using TH-CDMA based anti-collision scheme. This paper focuses on the back-end design consideration of such an RFID system with the deployment of high-level modeling techniques, accompanying a technical comparison of physical-level description, hardware-based emulation, and software-based simulation. A new rapid-prototyping simulation system was constructed to evaluate the robustness of a multiplexed RFID link system with more than 1,000 channels in the presence of field disturbances, and the design parameters of the back-end digital signal processing that dominated anti-collision performance were explored. Finally, the derived optimum parameters were applied to the design of a back-end digital integrated circuit to be installed in collision-resistive transponder circuitry.

Object caching is a common feature in the scalable distributed object systems. Fine-grained replication optimizes the performance and resource utilization in object caching by enabling a remote object-oriented application to be partially and incrementally on-demand replicated in units of cluster. Despite these benefits, the lack of common and simple implementation framework makes the fine-grained replication scheme not extensively used. This paper proposes the novel frameworks for dynamic, transparent, partial and automatically incremental replication of distributed Java objects based on three techniques that are lazy-object creation, proxy and hook. One framework enables the fine-grained replication of server-side stateful in-memory application, and the other framework enables the fine-grained replication of server-side stateless in-memory application, client-side program, or standalone application. The experimental evaluation demonstrates that the efficiency in terms of response time of both frameworks are relatively practical to the extent of a local method invocation.

In this paper, we propose a high speed Preamble Searcher suitable for the RACH (Random Access Channel) structure in WCDMA reverse link receivers. Unlike IS-95, WCDMA system uses the AISMA (Acquisition Indication Sense Multiple Access) scheme. Because of the time limit between RACH preamble transmission and AI (Acquisition Indicators), and the restriction on the number of RACH signatures assigned to RACH preamble, fast acquisition is required for efficient operation. The Preamble Searcher proposed in this paper is designed for 2-antenna systems; it adopts the FHT (Fast Hadamard Transform) algorithm that has the radix-2 16 point FFT (Fast Fourier Transform) structure. The acquisition speed using FHT is 32 times faster than the conventional method that correlates each signature. Based on this fast acquisition scheme, we improved the acquisition performance by calculating correlation up to 4096 chips of the total preamble length.

A novel method to simplify decision functions of support vector machines (SVMs) is proposed in this paper. In our method, a decision function is determined first in a usual way by using all training samples. Next those support vectors which contribute less to the decision function are excluded from the training samples. Finally a new decision function is obtained by using the remaining samples. Experimental results show that the proposed method can effectively simplify decision functions of SVMs without reducing the generalization capability.

This work presents an application of the previously proposed Support Vector Machines Based Generalized Predictive Control (SVM-Based GPC) method [1] to the problem of controlling chaotic dynamics with small parameter perturbations. The Generalized Predictive Control (GPC) method, which is included in the class of Model Predictive Control, necessitates an accurate model of the plant that plays very crucial role in the control loop. On the other hand, chaotic systems exhibit very complex behavior peculiar to them and thus it is considerably difficult task to get their accurate model in the whole phase space. In this work, the Support Vector Machines (SVMs) regression algorithm is used to obtain an acceptable model of a chaotic system to be controlled. SVM-Based GPC exploits some advantages of the SVM approach and utilizes the obtained model in the GPC structure. Simulation results on several chaotic systems indicate that the SVM-Based GPC scheme provides an excellent performance with respect to local stabilization of the target (an originally unstable equilibrium point). Furthermore, it somewhat performs targeting, the task of steering the chaotic system towards the target by applying relatively small parameter perturbations. It considerably reduces the waiting time until the system, starting from random initial conditions, enters the local control region, a small neighborhood of the chosen target. Moreover, SVM-Based GPC maintains its performance in the case that the measured output is corrupted by an additive Gaussian noise.

Nonlinear modeling of complex irregular systems constitutes the essential part of many control and decision-making systems and fuzzy logic is one of the most effective algorithms to build such a nonlinear model. In this paper, a new approach to fuzzy modeling is proposed. The model considered herein is the well-known Sugeno-type fuzzy system. The fuzzy modeling algorithm suggested in this paper is composed of two phases: coarse tuning and fine tuning. In the first phase (coarse tuning), a successive clustering algorithm with the fuzzy validity measure (SCFVM) is proposed to find the number of the fuzzy rules and an initial fuzzy model. In the second phase (fine tuning), a moving genetic algorithm with partial encoding (MGAPE) is developed and used for optimized tuning of membership functions of the fuzzy model. Two computer simulation examples are provided to evaluate the performance of the proposed modeling approach and compare it with other modeling approaches.