Organic nonlinear optical crystal 4-(p-dimethylaminostyryl)-1-methylpridinium tosylate (DAST) has a larger electro-optic (EO) coefficient than that of LiNbO3 crystal. Thus, DAST is a promising material for EO switching device. To use its large EO coefficient effectively, a waveguide structure is desirable. We have successfully fabricated two types of DAST crystal optical channel waveguide. One is a serially grafted waveguide combining a DAST and a transparent polymer by using the combination of standard photo-process and reactive ion-etching (RIE). Because DAST has large optical loss, parts of the waveguide should be composed of transparent polymer with a serially grafted structure with DAST. This structure reduced not only a propagation loss but also input/output losses. This serially graft waveguide fabrication technique for active organic crystal is available to many types of crystals with device function. The other is a channel waveguide made by a photo-bleaching technique. The cladding part of DAST waveguide was photo-bleached by irradiation of UV light. Under and over cladding layer were composed with UV-cured resin that did not dissolve the DAST crystal. This technique is very convenient for making DAST waveguide because of its simple procedure to make core-cladding structure of DAST compared to standard photo-process and RIE.

Many researches have been conducted on the recognition of Thai characters. Different approaches, such as neural network, syntactic, and structural methods, have been proposed. However, the success in recognizing Thai characters is still limited, compared to English characters. This paper proposes an approach to recognize the printed Thai characters using the hybrid of global feature, local features, fuzzy membership function and the neural network. The global feature classifies all characters into seven main groups. Then the local features and the neural network are applied to identify the characters.

It have been one open and significant topic for real-time applications to enhance the processing-speed of Boltzmann machines for long time. One effective way of solution of this problem is the augmentation of probability of neurons' state move. In this paper, a novel method, called a rejectionless method, was proposed and introduced into the Boltzmann machines for this augmentation. This method has a feature of independence on the ratio of neurons' state move. The efficiency of this method for speed-up was confirmed with the experiments of TSP and graph problem.

We consider diagnosability of butterfly networks under the comparison approach proposed by Maeng and Malek. Sengupta and Dahbura discussed characterization of diagnosable systems under the comparison approach, and designed a polynomial time algorithm to identify the faulty processors. However, for a general system, it is not algorithmically easy to determine its diagnosability. This paper proposes two comparison schemes for generating syndromes on butterfly networks, and determine the diagnosability of the network.

In this paper, we study system-level diagnosis under the comparison approach proposed by Maeng and Malek. Sengupta and Dahbura designed an O(n5) time diagnosis algorithm for identifying all faulty nodes in general graphs (n is the number of nodes in a system). We consider diagnosis on a butterfly network BF(k,r) and propose O(k2 n) time diagnosis algorithms for locating all faulty nodes in BF(k,r).

Services that operate normally, independently, will behave differently when simultaneously initiated with another service. This behavior is called a feature interaction. A feature interaction, where the next state can not be determined uniquely for one event, is called a non-determinacy feature interaction. To detect the interaction, judgment has to be made as to whether the state, where the non-determinacy occurs, is reachable from the initial state or not. For the judgment, many methods have been proposed. But, still now, it is required huge computation time to judge the reachability. This paper proposes a new method to test the reachability using a little knowledge elicited beforehand. By using the proposed method computation time was reduced drastically. Besides, by applying the proposed method to a benchmark, the proposed method was confirmed to be effective and reasonable.

The Bach compiler is a behavioral synthesis tool, which synthesizes RT-level circuits from behavioral descriptions written in the Bach C language. It shortens the design period of LSI and helps designers concentrate on algorithm design and refinement. In this paper, we propose methods for optimizing the area and performance of algorithms described in Bach C. In our experiments, we optimized a Viterbi decoder algorithm using our proposed methods and synthesized the circuit using the Bach compiler. The conclusion is that the circuit produced using Bach is both smaller and faster than the hand-coded register transfer level (RTL) design. This proves that the Bach compiler produces high-quality results and the Bach C language is effective for describing the behavior of hardware at a high-level.

This paper proposes a method for mapping a finite state machine (FSM) into a two-dimensional array of LUTs, which is a part of our plastic cell architecture (PCA). LSIs based on the PCA have already implemented as asynchronous devices. Functions that run on the LSIs must also be asynchronous. In order to make good use of the LSIs, a system that translates functions into circuit information for the PCA is needed. We introduce a prototype system that maps an asynchronous FSM onto the PCA. First, a basic mapping method is considered, and then we create three methods to minimize circuit size. Some benchmark suites are synthesized to estimate their efficiency. Experimental results show that all the methods can map an asynchronous FSM onto the PCA and that the three methods can effectively reduce circuit size.

In this paper, we propose a probabilistic approach to derive an approximate polyhedral description from range data. We first compare several least-squares-based methods for estimation of local normal vectors and select the most robust one based on a reasonable noise model of the range data. Second, we extract the stable planar regions from the range data by examining the distributions of the local normal vectors together with their spatial information in the 2D range image. Instead of segmenting the range data completely, we use only the geometries of the extracted stable planar regions to derive a polyhedral description of the range data. The curved surfaces in the range data are approximated by their extracted plane patches. With a probabilistic approach, the proposed method can be expected to be robust against the noise. Experimental results on real range data from different sources show the effectiveness of the proposed method.

In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache. " The cache attempts to reuse tag-comparison results for avoiding unnecessary tag checks. Execution footprints are recorded into an extended BTB (Branch Target Buffer). In our evaluation, it is observed that the energy for tag comparison can be reduced by more than 90% in many applications.

We give an overview of the computational complexity of linear and mesh-connected cellular and iterative arrays with respect to well known models of sequential and parallel computation. We discuss one-way communication versus two-way communication, serial input versus parallel input, and space-efficient simulations. In particular, we look at the parallel complexity of cellular arrays in terms of the PRAM theory and its implications, e.g., to the parallel complexity of recurrence equations and loops. We also point out some important and fundamental open problems that remain unresolved. Next, we investigate the solvability of some reachability and safety problems concerning machines operating in parallel and cite some possible applications. Finally, we briefly discuss the complexity of the "commutativity analysis" technique that is used in the areas of parallel computing and parallelizing compilers.

The stateless-based cache invalidation schemes for wireless environments can be categorized into either asynchronous or synchronous cache invalidation according to the broadcasting way of invalidation report. However, if the asynchronous cache invalidation scheme attempts to support local processing of read-only transaction, a critical problem may occur; the asynchronous invalidation reports provide no guarantee of waiting time for mobile transactions requesting commit. To solve this problem, the server in our approaches broadcasts two kind of messages, asynchronous invalidation report to reduce transaction latency and periodic guide message to avoid the uncertainty of waiting time for the next invalidation report. This paper presents a simulation-based analysis on the performance of the suggesting algorithms. The simulation experiments show that the local processing algorithms of read-only transaction based on asynchronous cache invalidation scheme get better response time than the algorithm based on synchronous cache invalidation scheme.

A fast, low-power 16-bit adder, 32-word register file and 512-bit cache SRAM have been developed using 0.25-µm GaAs HEMT technology for future multi-GHz processors. The 16-bit adder, which uses a negative logic binary look-ahead carry structure based on NOR gates, operates at the maximum clock frequency of 1.67 GHz and consumes 134.4 mW at a supply voltage of 0.6 V. The active area is 1.6 mm2 and there are about 1,230 FETs. A new DC/DC level converter has been developed for use in high-speed, low-power storage circuits such as SRAMs and register files. The level converter can increase the DC voltage, which is supplied to an active-load circuit on request, or supply a minimal DC voltage to a load circuit in the stand-by mode. The power dissipation (P) of the 32-word register file with on-chip DC/DC level converters is 459 mW, a reduction to 25.2% of that of an equivalent conventional register file, while the operating frequency (fc) was 5.17 GHz that is 74.8% of fc for the conventional register file. P for the 512-bit cache SRAM with the new DC/DC level converters is 34.3 mW, 89.7% of the value for an equivalent conventional cache SRAM, with the read-access time of 455 psec, only 1.1% longer than that of the conventional cache SRAM.

One of uncompromising requirements from portable computing is energy efficiency, because that affects directly the battery life. On the other hand, portable computing will target more demanding applications, for example moving pictures, so that higher performance is still required. Cache memories have been employed as one of the most important components of computer systems. In this paper, we briefly survey architectural techniques for high performance, low power cache memories.

The explosive growth of World Wide Web usage is causing a number of performance problems, including slow response times, network congestion, and denial of service. Web site that has a huge number of accesses and requires high quality of services, such as a site offering hosting services, or content delivery services, usually uses a cache server to reduce the load on the original server offering the original content. To increase the throughput of the caching process and to improve service availability, multiple cache servers are often positioned in front of the original server. This requires a switch to direct incoming requests to one of the multiple cache servers. In this paper, we propose a routing algorithm for such a switch in front of clustered multiple cache servers and evaluate its performance by simulation. The results show that our routing algorithm is effective when content has request locality and a short period of validity, for example, news, map data, road traffic data, or weather information. We also identify points to consider when the proposed algorithm is applied to a real system.

In this article, a hierarchical classifier is proposed for classification of ground-cover types of a satellite image of Kangaroo Island, South Australia. The image contains seven ground-cover types, which are categorized into three groups using principal component analysis. The first group contains clouds only, the second consists of sea and cloud shadow over land, and the third contains land and three types of forest. The sea and shadow over land classes are classified with 99% accuracy using a network of threshold logic units. The land and forest classes are classified by multilayer perceptrons (MLPs) using texture features and intensity values. The average performance achieved by six trained MLPs is 91%. In order to improve the classification accuracy even further, the outputs of the six MLPs were combined using several committee machines. All committee machines achieved significant improvement in performance over the multilayer perceptron classifiers, with the best machine achieving over 92% correct classification.

This paper presents a high resolution long array thermal ink jet (TIJ) printhead which has been developed and demonstrated to operate successfully by combining two functional Si wafers, a bubble generating heater plate fabricated using LSI process and a channel plate fabricated using Si bulk micromachining technology. The heater plate consists of logic LSIs, high voltage MOS transistor, polycrystalline Si (Poly Si) heating resistor and polyimide protective layer. The polymide layer is patterned by O2 plasma reactive ion etching (RIE) and is applicable to high resolution heater array. The Si channel plate consists of an ink chamber and an ink inlet formed by KOH etching, and a nozzle formed by inductively coupled plasma RIE (ICP RIE). The nozzle formed by RIE has squeezed structures which contribute to high energy efficiency of drop ejector and therefore successful ejection of small ink drop. These two wafers are directly bonded by using a novel electrostatic bonding of full-cured polyimide to Si. The adhesive-less bonding provided an ideal shaped small nozzle orifice. And also, the bonding method enabled to use an on-chip LSI wafer because of the contamination free material and the suitable processing conditions (low temperature). The bonded wafer is diced to form printhead chip. No delamination or displacement of the chip was observed even though the chip was subjected to thermal stress during assembly process. This is because of no difference in thermal expansion coefficient between both chips (Si and Si). And therefore it is suitable for long chip concept. With the above technologies, we have fabricated a 1.3" long printhead with 1024 nozzles having a 800 dots per inch (dpi) resolution, a 2.7 pl. ink drop volume, 14 m/sec. ink drop velocity and 18 kHz jetting frequency. And we have confirmed high speed printing and high quality printing.

As the network speed becomes faster and requirements about various services are increased, a number of groups are currently developing technologies aimed at evolving and enhancing the capabilities of existing network. A Next-Generation Network (NGN) is defined as a hybrid telecommunications network that employs new distributed processing techniques to provide all types of services. By integrating the Intelligent Network (IN) technology and the Mobile Agent (MA) technology we can support service flexibility and service portability in NGN. In this paper, we propose a caching-based mobile agent model for NGN and analyze the performance of this model. The mobile agent technology increases the service portability and the caching strategy does the service reusability. Each Physical Entity (PE) has MAs within their repository through the caching strategy and processes service requests from users without the control of the central system such as Service Control Point (SCP). Therefore, we can decrease the total network load and the response time for user requests.

Fiber-optic MEMS which is fabricated by combining direct photo-lithography of optical fiber and silicon micro-machining is proposed. Preliminary results of micro-machining of optical fiber and variable telecommunication devices are presented.

Support vector machines (SVMs), newly introduced in the 1990s, are promising approach to pattern recognition. They are able to handle linearly nonseparable problems without difficulty, by combining the maximal margin strategy with the kernel method. This paper addresses a novel SVM-based classification scheme of land cover from polarimetric synthetic aperture radar (SAR) data. Polarimetric observations can reveal existing different scattering mechanisms. As the input into SVMs, the polarimetric feature vectors, composed of intensity of each channel, sometimes complex correlation coefficients and textural information, are prepared. Classification experiments with real polarimetric SAR images are satisfactory. Some important properties of SVMs, for example the relation between the number of support vectors and classification accuracy, are also investigated.