A new transmission line structure is presented in this work for advanced CMOS processes. This structure has a high quality factor and low attenuation. It allows slow-waves to propagate which results in low dispersion for a given characteristic impedance. It is also designed to satisfy the stringent density requirements of advanced CMOS processes. A model is developed to characterize this structure by analyzing the physical current flowing in the substrate and the shield structure. Test structures were fabricated using CMOS 90 nm process technology with measurements made up to 110 GHz using a transmission-reflection module on a network analyzer. The results correspond well to the proposed model.

This paper presents a family of rate-one quasi-orthogonal space-time block codes (QO-STBCs) for any number of transmit antennas. Full diversity of the proposed QO-STBCs is achieved via the use of constellation rotation. When the number of transmit antennas is even, these codes are delay "optimal." This property along with the quasi-orthogonality one allows the codes to have low decoding complexity. Besides, by applying lookup tables into the detection methods presented in [1] and generalizing them, two low-complexity maximum-likelihood (ML) decoders for the proposed QO-STBCs and for other existing QO-STBCs, called PMLD and QMLD, are obtained. Simulation results are provided to verify the bit error rate (BER) performances and complexities of both the proposed QO-STBCs and the proposed decoders.

Viable techniques such as dynamic voltage scaling (DVS) provide a new design technique to balance system performance and energy saving. In this paper, we extend previous works on task assignment problems for a set of linear-pipeline tasks over a set of processors. Different from previous works, we revisit the problems with two additional system factors: deadline and energy-consumption, which are key factors in real-time and power-aware computation. We propose an O(nm2) time complexity algorithm to determine optimal task-assignment and speed-setting schemes leading to minimal energy consumption, for a given set of m real-time tasks running on n identical processors (with or without DVS supports). The same result can be extended to a restricted form of heterogeneous processor model. Meanwhile, we show that on homogeneous processor model more efficient algorithms can be applied and result in time complexity of O(m2) when m ≤ n. For completeness, we also discuss cases without contiguity constraints. We show under such cases the problems become at least as hard as NP-hard.

As a result of the growth of sensor-enabled mobile devices, in recent years, users can utilize diverse digital contents everywhere and anytime. However, the interfaces of mobile applications are often unnatural due to limited computational capability, miniaturized input/output controls, and so on. To complement the poor user interface (UI) and fully utilize mobility as feature of mobile devices, we explore possibilities for a new UI of mobile devices. This paper describes the method for recognizing and analyzing a user's continuous action including the user's various gestures and postures. The application example we created is mobile game called AM-Fishing game on mobile devices that employ the accelerometer as the main interaction modality. The demonstration shows the evaluation for the system usability.

The concept of LR(k) validity is represented as an abstract interpretation of a refinement of the derivation semantics of a given grammar. Also the algorithm of LR(k) parsing is represented as an abstract interpretation of the refined semantics. Such representations of LR formalisms provide us with more intuitive and easier means by which to understand LR parsing.

This paper presents an architecture and a synthesis method for compact numerical function generators (NFGs) for trigonometric, logarithmic, square root, reciprocal, and combinations of these functions. Our NFG partitions a given domain of the function into non-uniform segments using an LUT cascade, and approximates the given function by a quadratic polynomial for each segment. Thus, we can implement fast and compact NFGs for a wide range of functions. Experimental results show that: 1) our NFGs require, on average, only 4% of the memory needed by NFGs based on the linear approximation with non-uniform segmentation; 2) our NFG for 2x-1 requires only 22% of the memory needed by the NFG based on a 5th-order approximation with uniform segmentation; and 3) our NFGs achieve about 70% of the throughput of the existing table-based NFGs using only a few percent of the memory. Thus, our NFGs can be implemented with more compact FPGAs than needed for the existing NFGs. Our automatic synthesis system generates such compact NFGs quickly.

In 2004, Tsuji and Shimizu proposed a one-time password authentication protocol, named 2GR (Two-Gene-Relation password authentication protocol). The design goal of the 2GR protocol is to eliminate the stolen-verifier attack on SAS-2 (Simple And Secure password authentication protocol, ver.2) and the theft attack on ROSI (RObust and SImple password authentication protocol). Tsuji and Shimizu claimed that in the 2GR an attacker who has stolen the verifiers from the server cannot impersonate a legitimate user. This paper, however, will point out that the 2GR protocol is still vulnerable to an impersonation attack, in which any attacker can, without stealing the verifiers, masquerade as a legitimate user.

Wireless communications technology continues to change and yield new standards for satisfying the user demands. As a result, multiple standards coexist and wireless communications systems supporting different air interfaces cannot interact with one another. Software-defined radio is regarded as the most promising solution to cope with this problem. In this paper, we discuss the design considerations of SDR systems from a base station point of view and propose new architecture which meets the inherent requirements of SDR platform. We then introduce hardware/software of SDR platform we accomplished on the basis of the new architecture. In addition, the results of basic transmission and receiving performance are presented to prove the feasibility of the proposed platform as a base station.

In this paper, we propose a methodology for calculating on-chip temperature gradient and leakage power distributions. It considers the interdependence between leakage power and local temperature using a general circuit simulator as a differential equation solver. The proposed methodology can be utilized in the early stages of the design cycle as well as in the final verification phase. Simulation results proved that consideration of the temperature dependence of the leakage power is critically important for achieving reliable physical designs since the conventional temperature analysis that ignores the interdependence underestimates leakage power considerably and may overlook potential thermal runaway.

A multiple-source system for rendering the sound pressure distribution in a target region can be modeled as a multi-input-multi-output (MIMO) system with the inputs being the source strengths and the outputs being the pressures on multiple measuring points/sensors. In this paper, we propose a target-oriented acoustic radiation generation technique (TARGET) for sound field control. For the MIMO system of a given geometry, a series of basic radiation modes, namely, target-oriented radiation modes (TORMs) can be derived using eigenvector analysis. Different TORMs have different contributions to the system control gain, which is defined as the ratio of the acoustic energy generated in the target zone to the transmitter output power. The TARGET can be effectively applied to the sound reproduction and suppression, which correspond the generations of bright and dark zone respectively. In acoustically bright zone generation and sound beamforming, the highest-gain TORM can be employed to determine the optimal source strengths. In active noise control, the strengths of the secondary sources can be derived using low-gain TORMs. Simulation results show that the proposed method has better or comparable performance than the traditional techniques.

Network emulation system constructs a virtual network environment which has the characteristics of controllable and repeatable network conditions. This makes it possible to predict the correctness and performance of proposed new technology before deploying to Internet. In this paper we present a methodology for evaluating the correctness and performance of applications based on the PARNEM, a parallel discrete event network emulator. PARNEM employs a BSP based real-time event scheduling engine, provides flexible interactive mechanism and facilitates legacy network models reuse. PARNEM allows detailed and accurate study of application behavior. Comprehensive case studies covering bottleneck bandwidth measurement and distributed cooperative web caching system demonstrate that network emulation technology opens a wide range of new opportunities for examining the behavior of applications.

One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In MTCMOS circuit, voltage on virtual ground fluctuates due to a discharge current of a logic cell. This event affects to the cell delay and makes static timing analysis (STA) difficult. In this paper, we propose a delay modeling and static STA methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. This technique enables to calculate the cell delay considering the delay increase by the voltage fluctuation of virtual ground line. Experimental results show that the proposed methodology enables to estimate the cell delay and the critical path delay within 8% errors compared with SPICE simulation.

This paper presents a structural approach for synthesizing arbitrary multi-output multi-stage static CMOS circuits at the transistor level, targeting the reduction of transistor counts. To make the problem tractable, the solution space is restricted to the circuit structures which can be obtained by performing algebraic transformations on an arbitrary prime-and-irredundant two-level circuit. The proposed algorithm is guaranteed to find the optimal solution within the solution space. The circuit structures are implicitly enumerated via structural transformations on a single graph structure, then a dynamic-programming based algorithm efficiently finds the minimum solution among them. Experimental results on a benchmark suite targeting standard cell implementations demonstrate the feasibility and effectiveness of the proposed approach. We also demonstrated the efficiency of the proposed algorithm by a numerical analysis on randomly-generated problems.

Self-organized organic dye particles of micrometer and submicrometer size were prepared by utilizing a wetting/dewetting process of polar solvent on a hydrophilic glass substrate. The near-field scanning optical microscopy successfully identified near-field excited near-field fluorescence from single particles, however, the majority of the small particles with diameters around 2 µm or less did not show fluorescence under near-field observation. In contrast, far-field fluorescence, when excited by a polarized evanescent field, was observed, with the intensity depending on the excitation polarization, indicating that molecules' transition moment within dye particles was oriented parallel to the substrate surface. Single particle fluorescence spectrum consistently showed an identical sharp peak with a large redshift, indicating that the particles were composed of identical dye aggregates similar to J-aggregates. These observations suggest that the near-field at the probe tip was polarized parallel to the probe axis. Another observation, that molecules were oriented in a similar direction among adjacent particles, suggests that the dewetting process contributed to the alignment of the molecular orientation among adjacent particles, which further proves that the present specimen was formed by a self-organizing mechanism.

The I/Q unbalance which is generated by a non-ideal component is an inevitable physical phenomenon and leads to performance degradation when we implement a practical two-dimensional (2-D) modulation system. In this paper, we provide an exact and general expression involving the 2-D Gaussian Q-function for the SER/BER of arbitrary 2-D signaling with I/Q amplitude and phase unbalances over an additive white Gaussian noise (AWGN) channel by using the coordinate rotation and shifting technique. Through Monte Carlo simulations we verify our expression provided here for 16-star Quadrature Amplitude Modulation (QAM).

A compact representation of the Green function is proposed by applying the discrete wavelet concept in the k-domain, which can be used for the acceleration of scattered field calculations in integral equation methods. A mathematical expression of the Green function based on the discrete wavelet concept is derived and its characteristics are discussed.

We examined a Ti-diffused optical waveguide formed on a thin X-cut LiNbO3 substrate for a lower-drive-voltage modulator. Under the single-mode condition, optical mode-size decreases with LiNbO3 substrate thickness below 10 µm. A thin-sheet LiNbO3 modulator could achieve a low-drive-voltage of 1.3 V with a bandwidth of 15 GHz by adopting a narrow electrode-gap.

A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18 µm 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8 V, 25), a clock frequency of 266 MHz can be achieved.

We propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control with a dummy wordline and its feedback is also introduced to guarantee stable operation in a wide range of the supply voltage. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that a power reduction of 30% can be achieved at 100 MHz. In a 65-nm 64-Mb SRAM, a 74% power saving is expected at 1/6 of the maximum operating frequency. The performance penalty by the proposed scheme is less than 1%, and area overhead is 5.6%.

A radio synchronization technique that dispenses with GPS (Global Positioning System) for OFDM (Orthogonal Frequency Division Multiplexing)-based broadband networks is described. UMTS (Universal Mobile Telecommunications System) employs three main mechanisms, a node, transport channel and radio interface synchronization. The RNC (Radio Network Controller) is used as a key network component for the centralized synchronization mechanism. Here, we explore a more accurate and simpler asynchronous technique for broadband networks from the perspective of a distributed manner, where MSs (Mobile Stations) play an important role in timing adjustment. Propagation delay and the hierarchical synchronization mechanism are taken into account in the mathematical analysis.