This letter presents an iterative decision feedback channel estimation scheme for burst mode COFDM transmission. The feature of the proposed scheme is that the channel estimation using metrics comparison is applied to the initial stage of the iterative mechanism, which makes it possible to provide a reliable data stream at the initial stage. Computer simulation results show that the proposed approach provides better BER than the traditional iterative decision feedback channel estimation scheme irrespective of the number of iterations.

An electron transfer mediated amperometric enzyme biosensor based on a plasma-polymerized thin film of dimethylaminomethylferrocene (DMAMFc) is reported. A nanoscale thin polymer film containing a redox mediator was plasma-deposited directly onto an electrode with physisorbed glucose oxidase (GOD). Since the redox sites were introduced in the vicinity of the reaction centers of GOD, a highly efficient electron transfer system was formed in which almost all the reaction centers of GOD were connected to redox sites of the polymer matrix. The advantages of this strategy were: no need for prior or further chemical modification of the enzyme molecules, and simplicity of design compared with the use of a conventional polymer matrix. Moreover, the fact that the film deposition was performed using a microfabrication-compatible organic plasma promised great potential for high-throughput production of bioelectronic devices.

In 2004, Tsuji and Shimizu proposed a one-time password authentication protocol, named 2GR (Two-Gene-Relation password authentication protocol). The design goal of the 2GR protocol is to eliminate the stolen-verifier attack on SAS-2 (Simple And Secure password authentication protocol, ver.2) and the theft attack on ROSI (RObust and SImple password authentication protocol). Tsuji and Shimizu claimed that in the 2GR an attacker who has stolen the verifiers from the server cannot impersonate a legitimate user. This paper, however, will point out that the 2GR protocol is still vulnerable to an impersonation attack, in which any attacker can, without stealing the verifiers, masquerade as a legitimate user.

Frequency-domain equalization (FDE) based on the minimum mean square error (MMSE) criterion can significantly improve the BER performance of DS- and MC-CDMA systems in a severe frequency-selective fading channel. However, since the frequency-distorted signal cannot be completely equalized, the residual inter-code interference (ICI) limits the BER performance improvement. 4G systems must support much higher variable rate data services. Orthogonal multicode transmission technique has flexibility in offering variable rate services. However, the BER performance degrades as the number of parallel codes increases. In this paper, we propose an iterative frequency-domain soft interference cancellation (IFDSIC) scheme for multicode DS- and MC-CDMA systems and their achievable BER performances are evaluated by computer simulation.

As VLSI technology advances, delay variations will become more serious. Delay-insensitive asynchronous dual-rail circuits tolerate any delay variation, but their energy consumption is more than double that of the single-rail circuits because signal transitions occur every cycle in all bits regardless of the input bit pattern. However, in functional units, a significant number of input bits may not change from the previous input in many cases. In such a situation, calculation of these bits is not required. Thus, we propose a method, called unflip-bits control, makes use of the above situation, to reduce energy consumption. We evaluate the energy consumption and performance penalty for the method using HSPICE and the verilog-XL simulator, and compare the method with the conventional dual-rail circuit and a synchronous circuit. Our evaluation results reveal that the proposed asynchronous dual-rail circuit has a 12-60% lower energy consumption compared with a conventional asynchronous dual-rail circuit.

Recently, the number of multi-homed hosts is getting large, which are equipped with multiple network interfaces to support multiple IP addresses. Although there are several proposals that aim at bandwidth aggregation for multi-homed hosts, few of them support mobility. This paper proposes a new framework called AMS: Aggregate-bandwidth Multi-homing Support. AMS provides functions of not only bandwidth aggregation but also mobility by responding to the changes of the number of connections during communication without the support of underlying infrastructure. To achieve efficient data transmission, AMS introduces a function called address pairs selection to select an optimal combination of addresses of the peer nodes. We implemented AMS in the kernel of NetBSD and evaluated it in our test network, in which dummynet was used to control bandwidth and delay. The measured results showed that AMS achieved ideal bandwidth aggregation in three TCP connections by selecting optimal address pairs.

This paper presents a novel power estimation method for large and complex LSIs. The proposed method is based on simulation and is used for analyzing the ways in chip-scale gate-level circuits including processors and memory are affected by gated-clock power reduction and the voltage drop due to electrical resistance. The chip-scale power estimation based on simulation patterns generally takes enormous time. In order to reduce the time to obtain accurate estimation results based on simulation patterns, we introduce three approaches: "partitioning of target LSIs and simulation pattern," "memory modeling," and "processor modeling." After placing and routing, the target LSIs are partitioned into hierarchical blocks, memory, and processors. The power consumption of each hierarchical block is calculated by using the partitioned patterns generated from chip-scale simulation patterns. The power consumption of the processor and memory blocks is estimated by a method considering the static power consumption and the rate of LSI activity ratio. Experimental results for a commercial 0.18 µm-technology media processing chip show that the proposed method is 23 times faster than the conventional method without partitioning and that both the results are almost the same.

One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In MTCMOS circuit, voltage on virtual ground fluctuates due to a discharge current of a logic cell. This event affects to the cell delay and makes static timing analysis (STA) difficult. In this paper, we propose a delay modeling and static STA methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. This technique enables to calculate the cell delay considering the delay increase by the voltage fluctuation of virtual ground line. Experimental results show that the proposed methodology enables to estimate the cell delay and the critical path delay within 8% errors compared with SPICE simulation.

This paper introduces a common database, an evaluation framework, and its baseline recognition results for in-car speech recognition, CENSREC-3, as an outcome of the IPSJ-SIG SLP Noisy Speech Recognition Evaluation Working Group. CENSREC-3, which is a sequel to AURORA-2J, has been designed as the evaluation framework of isolated word recognition in real car-driving environments. Speech data were collected using two microphones, a close-talking microphone and a hands-free microphone, under 16 carefully controlled driving conditions, i.e., combinations of three car speeds and six car conditions. CENSREC-3 provides six evaluation environments designed using speech data collected in these conditions.

Ultra wideband (UWB) signal propagation was measured and characterized in comparison with narrowband in a passenger-car compartment, to accommodate the design of new wireless devices for the safety and comfort of passengers. Spatial distributions of UWB and narrowband path gain, delay profiles, and delay spreads within the compartment were derived from frequency-domain responses (from 3.1 to 10.6 GHz) measured with a vector network analyzer. Whereas narrowband channels resulted in a number of dead spots (deep fading points), UWB yielded none, though some frequency dispersion was inevitable. Fading depth versus occupied bandwidth was also derived, which indicated superiority of UWB over narrowband systems from the viewpoint of link budget. Comparison with two other environments was also made in the received energy contained in a given number of multipath components.

This paper deals with computation of parallel degree, PARAdeg, for (dataflow) program nets with SWITCH-nodes. Ge et al. have given the definition of PARAdeg and an algorithm of computing PARAdeg for program nets with no SWITCH-nodes. However, for program nets with SWITCH-nodes, any algorithm of computing PARAdeg has not been proposed. We first show that it is intractable to compute PARAdeg for program nets with SWITCH-nodes. To do this, we define a subclass of program nets with SWITCH-nodes, named structured program nets, and then show that the decision problem related to compute PARAdeg for acyclic structured program nets is NP-complete. Next, we give a heuristic algorithm to compute PARAdeg for acyclic structured program nets. Finally, we do experiments to evaluate our heuristic algorithm for 200 acyclic structured program nets. We can say that the heuristic algorithm is reasonable, because its accuracy is more than 96% and the computation time can be greatly reduced.

In this paper, the interpolation line search (ILS) algorithm to find the desirable step length in a numerical optimization method is investigated to determine the optimal saturation limits with non-smooth nonlinearities. The simple steepest descent algorithm is used to illustrate that the ILS algorithm can provide adequate reductions in an objective function at minimal cost with fast convergence. The power system stabilizer (PSS) with output limits is used as an example for a nonlinear controller to be tuned. The efficient computation to implement the ILS algorithm in the steepest descent method is available by using the hybrid system model with the differential-algebraic-impulsive-switched (DAIS) structure. The simulation results are given to show the performance improved by the ILS algorithm.

Petri nets have recently become widely accepted as a description method for biological pathways by researchers in computer science as well as those in biology. This paper gives an overview of Petri net formalisms to describe biological pathways and discusses their use in modelings and simulations for the systematic understandings of biological pathways. After reviewing the use of various types of Petri nets for the biological pathway modelings, we showed the examples that analyze fundamental properties of biological pathways using T-invariant, P-invariant, siphon, and trap. Applications of hybrid Petri nets for producing new biological hypotheses through simulations are also illustrated.

This paper considers Cyclic Job-Shop Scheduling Problems (CJSSP) extended from the Job-Shop Scheduling Problem (JSSP). We propose an evolutionary computing method to solve the problem approximately by generating the Petri net structure for scheduling. The crossover proposed in this paper employs structural analysis of Petri net model, that is, the crossover improves the cycle time by breaking the bottle-neck circuit obtained by solving a linear programming problem. Experimental evaluation shows the effectiveness of our approach.

Pneumatic pressure, which is easy enough to be handled in comparison with hydraulic pressure and is endowed with high safety, is available for a power source of a robot arm to be utilized in concert with human beings to do various types of work. But pneumatic pressure is so low in comparison with hydraulic pressure that an air cylinder having a diameter long enough and stroke wide enough is required to obtain great output power. In this study, therefore, the investigation was made with layout of air cylinders and transmission mechanisms of the motion power directed toward the driving joints to be followed by development of a new humanoid robot arm with seven degrees of freedom in which air cylinders are compactly incorporated. To be concrete with this, contrivance was made with an endoskeleton structure allowing almost all of the structure materials of the individual arm joints to be shared by the air cylinder with incorporation of the air cylinder in the axes of the upper arm joint and forearm joints by paying attention to the fact that the cylinder itself has high strength. The evaluation experiments driving the robot arm referred to above were conducted by means of I-PD control. The results suggested that the mechanism of the robot with seven degrees of freedom having pneumatic actuators proposed in this study is useful as the humanoid robot arm. The quick and accurate motions were accomplished with I-PD control which is relatively easy to be dealt with but not suitable for non-linear actuator system.

We have developed a code-division-multiplexing (CDM) transmission scheme for future road-vehicle communication systems, which uses cyclic shifted-and-extended (CSE) codes generated from a basic code with superior auto-correlation characteristics. This paper proposes to use a Quasi-Orthogonal (QO) sequence as the basic code. Its auto-correlation values are zero except at zero and middle shifts. When the CDM transmission is performed by the CSE codes based on the QO sequence, a desired correlation value is, at a receiver, interfered by the auto-correlation value at middle shift. Therefore, an elimination technique for the interfered correlation value is proposed and realizes zero cross-correlation characteristics within the cyclical shift interval. The new CDM transmission scheme based on the proposed scheme is evaluated by computer simulations in terms of the bit-error-rate performance.

This paper overviews the high-speed power-line communication (PLC) technology, and the related standardization and regulatory activities are described. PLC modems of 200 Mbps class become a practical use stage in the West, and the standardization activity is active now. The discussion for deregulation is being continued in also Japan, and regulation values have been proposed. Another topic in this paper is a sensor network application of PLC, which is an indoor fine-grained localization system by acoustic Direct-Sequence Code Division Multiplexed (DS-CDM) signals. The obtained average accuracy of the localization in a 4 m2 plane was 1 cm if there was no obstacle. To realize the localization system, some novel ideas, such as PLC speakers, a synchronization method based on the zero-crossing timing of the mains frequency, and integrated wired/wireless PLC, are introduced.

Recently, Dutta and Barua proposed provably secure constant round authenticated group key agreement protocols in dynamic scenario. In this letter, we show that their Leave Protocol does not provide forward secrecy, that is, a leaving user can still obtain the new session key used in subsequent sessions.

In this paper, the relationship between correlation interval (CI) and estimate is investigated. Then a special correlation interval is explored that is adaptive to all levels of signal-to-noise ratio (SNR) and velocity conditions, and the mean square error is deduced. Finally, we propose an iterative algorithm that achieves the special correlation interval and calculates the Doppler spread by increasing the resolution on time-domain iteratively. Simulation results show that compared with conventional schemes, performance of the proposed algorithm is basically independent of velocity variation and less sensitive to SNR, especially in low SNR environments. It achieves high accurate estimation directly without any post-rectification.

This paper describes a new low-power write driver circuit for mobile hard disk drive preamplifiers. To achieve low power consumption, we developed a write driver circuit with a single-stage MOS transistor as the current driver, which both switches and controls the write current. We also developed a reflection cancellation method to suppress the distortion of the write current waveform during write transition. Fabricated using 0.35-µm SOI-BiCMOS technology, this write driver circuit consumes low power, 380 mW (at 100 MHz).