The selection method of the moment of inertia of the flywheel in a digital measurement system of torque-speed curve plotting for a kind of motor is presented. The selection standards of the moment of inertia and the map displaying the operating ranges of the measurement system are shown. The selection procedure of the moment of inertia is also shown.

This paper describes the waveform relaxation (WR) algorithm with the under relaxation method based on the virtual state formulation (VSF) technique and the effect of multirate behavior in this algorithm. First, we present the virtual state relaxation method using VSF technique. Next, we introduce the VSF method into WR algorithm in order to exploit the multirate behavior. Furthermore, we construct the relaxation-based circuit simulator DESIRE2 and apply this simulator to the transient analysis of MOS circuits. Finally, we show that the present technique enables to use efficiently the multirate integration method in VSR and reduce the total simulation time without losing the waveform accuracy.

This paper proposes parallel VLSI processors for robotics based on multiple processing elements organized around multiple bus interconnection networks. The advantages of multiple bus interconnection networks are generality, simplicity of implementation and capability of parallel communications between processing elements, therefore it is considered to be suitable for parallel VLSI systems. We also propose the optimal scheduling formulated in an integer programming problem to minimize the delay time of the parallel VLSI processors.

An integrated CAD/CAM system for MMIC development has been firstly realized, which consists of electron beam direct drawing, microwave circuit simulator, pattern generator and RF &DC on-wafer automatic measurement subsystems, connected through an Ethernet LAN. The system can develop not only new MMICs and their element devices, but also their accurate simulation models quickly and efficiently. Preliminary successful applications of this system have been demonstrated by DC-HFET with a 0.25 µm T-shaped gate electrode and MMIC low-noise amplifiers operating at X- and L-bands.

This paper discusses and evaluates, from the viewpoints of definition, analysis, and performance, frequency assignment schemes that enable the efficient assignment of multiple-bandwidth carriers on the transponder in SCPC/FDMA systems with demand assignment operation. The system considered handles carriers of two different bandwidths, and assigns only consecutive slots on the transponder band to broadband carriers. Three types of frequency assignment schemes are proposed, each of which incorporates one or both of two assignment concepts: (1) pre-establishment of assignment priorities on the transponder band, and (2) establishment of broadband slots to guide broadband carrier assignment. Following a definition of the schemes, equations are derived to theoretically analyze performance factors such as call loss for the narrowband and broadband carriers, and system utilization efficiency. Finally, theoretical performance calculated for various traffic and system conditions are presented and evaluated, for the purpose of comparison between the three schemes. Computer simulation results are also presented, to demonstrate the accuracy of the derived equations and to supply data for models too large for theoretical computation. Main results obtained are as follows. (1) Regardless of traffic or system conditions, the assignment scheme incorporating both assignment priorities and broadband slots shows the best performance in terms of broadband call loss and system utilization efficiency. (2) The establishment of broadband slots improves performance when the ratio of broadband traffic to the total traffic volume is high, but worsens performance when the narrowband traffic ratio is higher. (3) All aspects of performance improve with the increase of the total number of assignable slots on the transponder band.

Information geometry is a new powerful method of information sciences. Information geometry is applied to manifolds of neural networks of various architectures. Here is proposed a new theoretical approach to the manifold consisting of feedforward neural networks, the manifold of Boltzmann machines and the manifold of neural networks of recurrent connections. This opens a new direction of studies on a family of neural networks, not a study of behaviors of single neural networks.

The purpose of the present paper is to review a state of the art of nonlinear analysis with the self-validating numerical method. The self-validating numerics based method provides a tool for performing computer assisted proofs of nonlinear problems by taking the effect of rounding errors in numerical computations rigorously into account. First, Kantorovich's approach of a posteriori error estimation method is surveyed, which is based on his convergence theorem of Newton's method. Then, Urabe's approach for computer assisted existence proofs is likewise discussed. Based on his convergence theorem of the simplified Newton method, he treated practical nonlinear differential equations such as the Van der Pol equation ahd the Duffing equation, and proved the existence of their periodic and quasi-periodic solutions by the self-validating numerics. An approach of the author for generalization and abstraction of Urabe's method are also discribed to more general funcional equations. Furthermore, methods for rigorous estimation of rounding errors are surveyed. Interval analytic methods are discussed. Then an approach of the author which uses rational arithmetic is reviewed. Finally, approaches for computer assisted proofs of nonlinear problems are surveyed, which are based on the self-validating numerics.

A tag-partitioned join algorithm is described. The algorithm partitions only one relation, while other partition-based algorithms partition both relations. It is performed as the joinable tuples of one relation are rearranged and some of them are duplicated according to the original sequence of the join attribute values of the other relation. To do this, the algorithm first finds the positions of all the tuples of the other relation which are joinable with each tuple of one relation, and then partitions joinable tuples of one relation into buckets by using the positions found. Final joining is performed on the partitioned relation and the other relation. We analyze and compare the performance of the algorithm with that of other partition-based join algorithms. The comparison shows that our method is better than other partition-based methods under the practical values of the analysis parameters.

Recently much attention has been devoted to the problem of translating a set of geometrical objects in a given direction, one at a time, without allowing collisions between the objects. This paper studies the translation problem in three dimensions on a set of c-oriented faces", that is, the faces whose bounding edges have a constant number c of orientations. We solve the problem in O(N log2 NK) time and O(N log N) space, where N is the total number of edges of the faces and K is the number of edge intersections in the projection plane. As an intermediate step, we also solve a problem related to ray-shooting. The algorithm for translating c-oriented faces finds uses in computer graphic systems.

The problems of cache coherency in multiprocessor systems are directly related to their architectural structures. Small scale multiprocessor systems have focused on the use of bus based memory interconnection networks using centrally shared memory and a sequential consistency model for coherency. This has limited scalability to but a few tens of processors due to the limited bus bandwidth used for both coherency updates and memory traffic. Recently, large scale multiprocessor systems have been proposed that use general interconnection networks and distributed shared memory. These architectures have been proposed using weak consistency models and various directory map schemes to hide the overhead for coherency maintenance within the memory hieratchy, interconnection network or process context switch latencies. The coherency and memory traffic are still maintained over the same interconnection network. In this paper, we present the architecture of a new general purpose medium scale multiprocessor system. This Cache Coherent Multiprocessor System (C2MP), supports distributed shared memory using a general memory interconnection network for memory traffic and a separate bus based coherency interconnection network for coherency maintenance. Through the use of a special directory based coherency protocol and cache oriented distributed coherency controllers, direct cache-to-cache coherency maintenance is performed over the dedicated coherency bus. This minimizes coherency updates to only those processor nodes needing coherency maintenance. An aggressive sequential coherncy model is used, which reduces the hardware penalty to support an ideal sequential consistency programmers model. The system can scale up to 256-512 processors depending on the degree of shared data and is expected to have higher per processor utilization in this range than currently proposed medium and large scale multiprocessor systems. The C2MP system is analyzed utilizing a Generalized Timed Petri-Net model of a processor node. A stochastic model for internode interactions over the general memory interconnection network and coherency bus are used . The model of the proposed architecture is analyzed under steady-state conditions for varying system work load parameters.

This paper proposes a Mean-Separated and Normalized Vector Quantizer with edge-Adaptive Feedback estimation and variable bit rates (AFMSN-VQ). The basic idea of the AFMSN-VQ is to estimate the statistical parameters of each coding block from its previous coded blocks and then use the estimated parameters to normalize the coding block prior to vector quantization. The edge-adaptive feedback estimator utilizes the interblock correlations of edge connectivity and gray level continuity to accurately estimate the mean and standard deviation of the coding block. The rate-variable VQ is to diminish distortion nonuniformity among image blocks of different activities and to improve the reconstruction quality of edges and contours to which the human vision is sensitive. Simulation results show that up to 2.7dB SNR gain of the AFMSN-VQ over the non-adaptive FMSN-VQ and up to 2.2dB over the 1616 ADCT can be achieved at 0.2-1.0 bit/pixel. Furthermore, the AFMSN-VQ shows a comparable coding performance to ADCT-VQ and A-PE-VQ.

Efficient probabilistic decision trees are required in various application areas such as character recognition. This paper presents a polynomial-time approximate algorithm for designing a probabilistic decision tree. The obtained tree is near-optimal for the cost, defined as the weighted sum of the expected test execution time and expected loss. The algorithm is advantageous over other reported heuristics from the viewpoint that the goodness of the solution is theoretically guaranteed. That is, the relative deviation of the obtained tree cost from the exact optimum is not more than a positive constant ε, which can be set arbitrarily small. When the given loss function is Hamming metric, the time efficiency is further improved by using the information theoretical lower bound on the tree cost. The time efficiency of the algorithm and the accuracy of the solutions were evaluated through computational experiments. The results show that the computing time increases very slowly with an increase in problem size and the relative error of the obtained solution is much less than the upper bound ε for most problems.

A new class of (m23m1,m2) 1-step majority-logic decodable double error correcting codes (1-step DEC codes) is described, where m is an odd integer. Combining this code with properly constructed (m1k1,k1) and (m,k2) 1-step DEC codes, a (m23(mk1)1,m23k1) 1-step DEC code and a (m23(mk2)1,m2) 2-step majority-logic decodable DEC code (2-step DEC code) are obtained, respectively. Considering computer memory applications, some practical 1 -and 2-step DEC codes with data-bit lengths of 24, 32, 64 and 72 are obtained by shortening the new codes, and are compared to existing majority-logic decodable DEC codes. It is shown that, for given data-bit lengths, new 2-step DEC codes have much better code rates than self-orthogonal DEC codes but slightly worse code rates than existing 2-step majority-logic decodable cyclic DEC codes (2-step cyclic DEC codes). However, parallel decoders of new 2-step DEC codes are much simpler than those of exisiting 2-step cyclic DEC codes, and are nearly as simple as those of 1-step DEC codes.

The encoding of high quality and super high definition images requires new approaches to the coding problem. The nature of such images and the applications in which they are used prohibits the introduction of perceptible degradation by the coding process. In this paper, we discuss techniques for the perceptually transparent coding of images. Although technically lossy methods, images encoded and reconstructed using these techniques appear identical to the original images. The reconstructed images can be postprocessed (e.g., enhanced via anisotropic filtering), due to the absence of structured errors, commonly introduced by conventional lossy methods. The compression, ratios obtained are substantially higher than those achieved using lossless means.

Resolving ambiguities in interpreting the user's utterances is one of the most fundamental problems in the development of a question-answering system. The process of disambiguating interpretations requires knowledge and inference functions on an objective task field. This paper describes a framework for understanding conversational language, using the multi-paradigm knowledge representation (frames" and rules") which represents concept hierarchy and causal relationships for an objective field. Knowledge of the objective field is used in the process to interpret input sentences as a model for the objective world. In interpreting sentences, a procedure judges preferences for interpretation candidates by identifying causal relationship with messages in the preceding context, where the causal relationship is used to supplement some shortage of information and to give either an affirmative or a negative explanation to the interpretation. The procedure has been implemented in an experimental question-answering system, whose current task is consultation in operating an electronic device. The experimental results are shown for a concrete problem involving resolving anaphoric references, and characteristics of the knowledge processing system are discussed.

The outputs of all gates in a circuit are assumed to be observable unber the highly observable condition, which is mainly based on the use of E-beam testers. When using the E-beam tester, it is desirable that the test set for a circuit is small and the test vectors in the test set can be applied in a successive and repetitive manner. For a combinational circuit, these requirements can be satisfied by modifying the circuit into a k-UCP circuit, which needs only a small number of tests for diagnosis. For a sequential circuit, however, even if the combinational portion has been modified into a k-UCP circuit, it is impossible that the test vectors for the combinational portion can always be applied in a successive and repetitive manner because of the existence of feedback loops. To solve this problem, the concept of k-UCP scan circuits is proposed in this paper. It is shown that the test vectors for the combinational portion in a k-UCP scan circuit can be applied in a successive and repetitive manner through a specially constructed scan-path. An efficient method of modifying a sequential circuit into a k-UCP scan circuit is also presented.

This paper addresses fault tolerance of a processor array that is reconfigurable by replacing faulty processors with spare processors. The fault tolerance of such a reconfigurable array depends on not only an algorithm for spare processor assignment but also the folloving factor of an organization of spare processors in the reconfigurable array: the number of spare processors; the number of processors that can be replaced by each spare processor; and how spare processors are connected with processors. We discuss a relationship between fault tolerance of reconfigurable arrays and their organizations of spare processors in terms of the smallest size of fatal sets and the reliability function. The smallest size of fatal sets is the smallest number of faulty processors for which the reconfigurable array cannot be failure-free as a processor array system no matter what reconfiguration is used. The reliability function is a function of time t whose value is the probability that the reconfigurable array is failure-free as a processor array system by time t when the best possible reconfiguration is used. First, we show that the larger smallest size of fatal sets a reconfigurable array has, the larger reliability function it has by some time. It suggests that it is important to maximize the smallest size of fatal sets in orer to improve the reliability function as well. Second, we present the best possible smallest size of fatal sets for nn reconfigurable arrays using 2n spare processor each of which is connected with n processors. Third, we show that the nn reconfigurable array previously presented in a literature achieves the best smallest size of fatal sets. That is, it is optimum with respect to the smallest size of fatal sets. Fourth, we present an uppr bound of the reliability function of the optimum nn reconfigurable array using 2n spare processors.

A new error rate formula for narrowband Differential Quaternary Phase Shift Keyed system in a Rayleigh fading channel is obtained in closed-form. The formula predicts a non-zero error probability for noiseless reception. As predicted, the computed error rates approach some constant or floor values as the signal-to-noise ratio is increased beyond a certain limit. In the presence of various Doppler frequency shifts, an IF filter bandwidth of about one times the symbol rate is found to lead to a minimum error probability prior to the appearence of the error rate floor.

Quantization of the impulse response coefficients due to finite word length causes the moments to deviate from their ideal values. This deviation is found to have a linear variation with the output roundoff noise of the filter realized in direct form. Since the zeros and poles of a given filter also move away from their designed locations due to quantization, we show a relation between the zeros and poles and the moments of the impulse response.

Roundness is one of the most important geometric measures for circular objects in the process of mechanical assembly. It is the amount of variation in a circular size which can be permitted. To compute roundness, the authors have already proposed an exact polynomial-time algorithm whose time complexity is O(n2). In this paper, we show that this roundness algorithm can be improved more efficiently, by introducing the deletion of the unnecessary points, in practical applications. In addition, the computational experience of this revised algorithm is also presented.