The process of room acoustic planning & design can be aided by Binaural Technology. To this end, a three-stage modelling process is proposed that consists of a "sound"-specification phase, a design phase and a work-plan phase. Binaural recording, reproduction and room simulation techniques are used throughout the three phases allowing for subjective/objective specification and surveillance of the design goals. The binaural room simulation techniques involved include physical scale models and computer models of different complexity. Some basics of binaural computer modelling of room acoustics are described and an implementation example is given. Further the general structure of a software system that tries to model important features of the psychophysics of binaural interaction is reported. The modules of the model are: outer-ear simulation, middle-ear simulation, inner-ear simulation, binaural processors, and the final evaluation stage. Using this model various phenomena of sound localization and spatial hearing, such as lateralization, multiple-image phenomena, summing localization, the precedence effect, and auditory spaciousness, can be simulated. Finally, an interesting application of Binaural Technology is presented, namely, a so called Cocktail-Party-Processor. This processor uses the predescribed binaural model to estimate signal parameters of a desired signal which may be distored by any type of interfering signals. In using this strategy, the system is able to even separate the signals of competitive speakers.

Fahlman and Lebiere's (FL) learning algorithm begins with a two-layer network and in course of training, can construct various network architectures. We applied FL algorithm to the same three-layer network architecture as a back propagation (BP) network and compared their generalization properties. Simulation results show that FL algorithm yields excellent saturation of hidden units which can not be achieved by BP algorithm and furthermore, has more desirable generalization ability than that of BP algorithm.

This paper describes a new method for verifying designs at the RTL with respect to their specifications at the functional level. The base of the verification method shown here is the translation of the specification and design representations to graph models, where the descriptions common to both representations have a symbolic representation. These symbol labeled graphs are then simplified and, by solving the all node-pair path expression problem for them, a pair of regular expressions is obtained for every two nodes in the graphs. The first regular expression in each pair represents the flow of control and the second one the flow of data between the corresponding nodes. The process of verification is carried out by checking whether or not every pair of regular expressions of the specification has a corresponding pair in the design.

We discuss fault tolerance of an information disseminating scheme, t-disseminate on a network with N processors, where each processor can send a message to t directions at each round. When N is a power of t+1 and at most tlogt+1N-1 (at most t) processors and/or edges have hailed, logt+1N+(f1)/t rounds (logt+1N+2 rounds) suffice for broadcasting information to all destinations from any source by t-disseminate. For a arbitrary N, logt+1N2f/t1 rounds (logt+1N+2 rounds) suffice for broadcasting information to all destinations from any source by t-disseminate if at most t(logt+1N1)/2 (at most t/2) processors and/or edges have failed.

This paper presents a new method for estimating both the parameters of a nonminimum phase system and its unknown input signal. An approximate inverse system method is used to estimate the unknown input signal, and then, by using a Kalman filter, approximately consistent parameter estimates of the nonminimum phase system can be obtained effectively. This method can be used to estimate the parameters of a nonminimum phase system and a minimum phase one in the case when the input signal is a white noise or an impulse sequence.

The pressure waveforms indicated on a catheter manometer system are subject to serious distortion due to the resonance of the catheter itself, or the compliance of a particular transducer. Although several methods have been proposed for improving those characteristics, they ahave never been put into practice. We have focused on the transfer function of the catheter manometer, and made a pilot system, using the natural observation method. This method has been suggested as a means of studying the structure of the instantaneous waveform. In this manner, we were able to increace the bandwidth in the ferquency domain and reduce the ringing in the time domain. Correction was performed automatically, using a step wave. Reproduction of the waveform with a flushing device, was a task of equal simplicity, that allowed us to estimate the system parameters so that the response waveform became step-like. In the experiment, our system provided distortion-free left-ventricular pressure waveform measurements and exact evaluation of the cardiac pumping system. The values obtained came much closer to the original figures arrived at by the catheter-tip manometer system.

An efficient reconstruction algorithm for diffraction tomography based on the modified Newton-Kantorovich method is presented and numerically studies. With the Fréchet derivative obtained for the Helmholtz equation, one can derive an iterative formula for getting an object function, which is a function of refractive index of a scatterer. Setting an initial guess of the object function to zero, the pth estimate of the function is obtained by performing the inverse Fourier transform of its spectrum. Since the spectrum is bandlimited within a low-frequency band, the algorithm does not require usual regularization techniques to circumvent ill-posedness of the problem. For numerical calculation of the direct scattering problem, the moment method and the FFT-CG method are utilized. Computer simulations are made for lossless and homogeneous dielectric circular cylinders of various radii and refractive indices. In the iteration process of image reconstruction, the imaginary part of the object function is set to zero with a priori knowledge of the lossless scatterer. Then the convergence behavior of the algorithm remarkably gets improved. From the simulated results, it is seen that the algorithm provides high-quality reconstructed images even for cases where the first-order Born approximation breaks down. Furthermore, the results demonstrate fast convergence properties of the iterative procedure. In particular, we can successfully reconstruct the cylinder of radius 1 wavelength and refractive index that differs by 10% from the surrounding medium. The proposed algorithm is also effective for an object of larger radius.

In this pater, we propose a method for matching of two images (stereo, motion stereo, etc.) using relaxation. We have already proposed an algebraic expression of line images using unit vectors, and matching method based on similarity measure between two image graphs. This similarity measure of images is insensitive to scaling, rotation, gray level modification and small motion between the two images in the case when we examine image registration or image matching. The approach based on the line structural similarity results in high rate of correspondence between nodes of the two images. In order to obtain higher rate of correspondence, we introduce a relaxation method when examine the degree of similarity between the two images. Our relaxation method improves a relational similarity of correspondence between two image graphs in an iterative manner. The relational similarity is defined as a correct likelihood of correspondence between nodes in consideration of connective relationship of the image graphs. Finally, we show several experimental results which confirm effectiveness of our approach.

This paper proposes a new fault tolerant intercommunication scheme for real-time operations and three new interconnection networks to construct a fault tolerant multi-processor system for pipeline processings. The proposed intercommunication scheme using bank memory switching technique has an advantage to make a fault tolerant pipeline system so that it can detect any failure caused in a processing element of the system. In addition, it can overcome conventional problems caused in interconnection circuits to flow data with one way direction such as a pipeline processing.

The newly developed GaAs-pin/SLM, that is structured with a GaAs-pin diode photodetector and a ferroelectric liquid crystal as the light phase modulator, shows the accumulative thresholding characteristic against the optical energy of the write-in pulse train. We experimentally investigate this characteristic and discuss its applications to optical parallel processings.

Unidirectional/Asymmetric error control codes have extensively been studied, not only from theoretical interest but from application to computer systems or communication systems. Recently, attention has been focused on detecting only d, not all, unidirectional errors, that is, d bits unidirectional error ditecting (d-UED) codes. Borden proposed an optimal nonsystematic d-UED code. This paper shows a new design method for cost-effective self-testing checker for the optimal d-UED code. The checking policy is to check whether condition of the Borden code satisfies or not. The proposed checker includes the parallel weight counter, the comparator and th e modulo adder in which new residue operation is defined and hence this makes the circuit self-testing. These circuits are designed to have all possible input patterns in order to satisfy self-testing property. Finally, the proposed checker has greatly reduced hardware amount compared to the existing one.

A new design method is proposed for realizing a hypercube network (HC) structured multicomputer system on a wafer using wafer-scale integration (WSI). The probability that an HC can be constructed on a wafer is higher in this method than in the conventional method; this probavility is called a construction probability. We adopt the FUSS method for the processor (PE) address allocation in our desing because it has a high success probability in the allocation. Even if the design renders the address allocation success probalility hegher, it is of no use if it makes either the maximum wiring length between PEs or the array size (wiring area) larger. A new wiring channel structure capable of connecting PEs on a wafer is proposed in this paper, where a channel, called a basic channel, is used. A one-dimensional-array sub-HC row network (RN) or column networks (CN) can be constructed using the basic channel. The sub-HC construction method, which embeds wirings into the basic channel, is also proposed. It requires almost the same wiring width as conventional method. However, it has an advantage in that maximum wiring length between PEs can be about half that of the conventional method. If PEs must be shifted in the case of PE defects, they can be shifted and connected to the basic channel using other PE shifting channels, and an RN or CN can be constructed. The maximum wiring length between PEs, array size, and construction probability will also be derived, and it will be shown that the proposed design is superior to the conventional one.

In this paper, the software structure for telecommunication user support are discussed, and it is proposed to apply knowledge processing technology to the software. Capabilities of telecommunications networks are becoming quite complicated, and the number of service items and parameters which have to be selected and memorized will become too large for telecommunications end users to make full use of the network capabilities. As such, more effort should be focused on assisting telecommunications end users to use the network and providing user friendly human interfaces of the network. However, this kind of software has additional type of requirements other than those for protocol handling software and call control software, and the realization of such support software has not yet been fully studied. To realize such support software, this paper stressed the realization of the user-system interface. Especially identified in this paper are meaning-based interpretation of user inputs to permit the handling of synonyms and multivocations, and a method to access the database in the support system without consideration of its data schema. To satisfy these objectives, this paper has proposed that the application data should be represented in both a character string and a meaning representation, and that the thesauruses should have the attribute-value relation. In line with these studies, an experimental system called CAPRIS (CAlling PRocedure Instruction System) was developed. It is used to assist the calling party in a telecommunications network to find an appropriate contact point depending on the purpose of the communication. Implementation of CAPRIS is completed and it was confirmed that all the functions described in this paper were actually realized. Some functional experiments were performed on CAPRIS, and the system was concluded to realize satisfactory user-friendliness.

Recently, Burch et al. proposed symbolic model checking method to verify sequential machines formally. The method, which is based on logic function manipulation using binary decision diagram, can handle large sequential machines that cannot be handled by the conventional techniques. The expressive power of Computational Tree Logic (CTL), which was used by Burch et al., is not very powerful, for example, CTL cannot describe repetition of events. This papers shows an extension of the symbolic model checking algorithm to Branching time regular temporal logic (BRTL), which has been proposed by the authors as an improvement of CTL in terms of expressive power. The implemented verifier based on the proposed algorithm could verify behaviors of a microprocessor composed of approximately 1,600 gates and 68 flipflops.

This paper presents the dynamics of heavy-ion induced latchup turn-on behavior in CMOS structures using a three-dimensional and transient device simulation. The three-dimensional effects of parasitic devices in a CMOS structure during latchup turn-on are discussed in detail when a heavy-ion strikes the CMOS structure. For different incident types, the dynamics of latchup turn-on behaviors are also simulated. Moreover, latchup immunities of the CMOS structure obtained by two- and three-dimensional calculations are compared for the different incident types. This result suggests that the rough relation between latchup immunity and heavy-ion incident energy can be estimated using a two-dimensional simulation.

An improved array architecture to realize fast access, low power dissipation, and wide operating margin, for the 16 Mbit DRAM is proposed. A high speed access is obtained by the fully embedded sense drive scheme for the RAS access time (tRAC), and the special page mode with the hierarchical I/O data bus lines and multi-purpose-register (MPR) for the column address access time (tCAA). A low power dissipation and wide operating margin are obtained by the improved twisted-bit-line (TBL) architecture with double dummy canceling. The 16 Mb DRAM using these architectures has 38 ns tRAC, 14 ns tCAA and 75 mA power dissipation at the typical condition.

The effectiveness of traffic shaping for VBR traffic is analyzed. Evaluation results prove that traffic shaping can improve link efficiency for most forms of bursty VBR traffic and that link efficiency gains of more than 250% can be expected without the shaping delay imposing any significant QOS deterioration. Traffic shaping increases the link efficiency to about 80% for traffic with short burst repetition periods. The traffic shaping techniques and analytical results described herein can be employed in the traffic management of future B-ISDN/ATM networks.

This paper describes the performance evaluation of the Translation Look-aside Buffer (TLB) for highly integrated microprocessors, especially concerning the TLB in the SPARC Reference MMU specification. The analysis covers configurations, the number of entries, and replacement algorithms for the instruction TLB and the data TLB, which are assumed to be practically integrated on one die. We also present performance improvement using a Page Table Cache (PTC). We evaluate some types of TLB configurations with software simulation and excute the Systems Performance Evaluation Cooperative (SPEC) programs.

This paper presents a protocol verification method which verifies that the behaviors of a protocol meet requirements. In this method, a protocol specification is expressed as Extended Finite State Machines (EFSM's) that can handle variables, and requirements are expressed using a branching-time temporal logic for a concise and unambiguous description. Using the acyclic expansion algorithm extended such that it can deal with EFSM's, the verification method first generates a state transition graph consisting of executable transitions for each process. Then a branching-time temporal logic formula representing a requirement is evaluated on one of the generated graphs which is relevant to the requirement. An executable state transition graph for each process is much smaller than a global state transition graph which has been used in the conventional verification techniques to represent the behaviors of the whole protocol system consisting of all processes. The computation for generating the graphs is also reduced to much extent for a large complex protocol. As a result, the presented method achieves efficient verification for requirements regarding a state of a process, transmission and reception of messages by a process, varibales of a process and sequences that interact among processes. The validity of the method is illustrated in the paper by the verification of a path-updating protocol for requirements such as process state reachability or fair termination among processes.

This paper describes a programming system, K-NET for the development of control software for flexible manufacturing systems composed of robots, numerically-controlled machines, transfer machines and automatic storage/retrieval systems. K-NET is based on a high-level Petri net which makes it simple to express operational functions such as synchronization, interlock and concurrence in sequence control. Petri net in K-NET is colored one in which tokens have attributes, and timed one which can provide a notion of stochastic time. K-NET provides many kinds of boxes having specific functions, and gates specified the firing condition and the token flow control with IF-THEN rules. On the other hand, procedural language can be also used for information processing. K-NET can support all development stages including general design, detailed design, programming and testing. K-NET has an editor to input control specifications expressed with Petri net; a simulator to verify edited specifications; a generator to convert the net to C source programs for a computer or to ladder diagrams for a programmable controller; a reporter to print control specifications; and a monitor to display controller status in real-time. K-NET has been used in the development of control software for an automated guided vehicle system, and results show a 2/3rds cost-saving over development with conventional methods in which only procedural language is used.