The element-by-element finite element method (EBE-FEM) combined with the preconditioned conjugate gradient (PCG) technique is employed in this paper to calculate the coupling capacitances of multi-level high-density three-dimensional interconnects (3DIs). All capacitive coupling 3DIs can be captured, with the effects of all geometric and physical parameters taken into account. It is numerically demonstrated that with this hybrid method in the extraction of capacitances, an effective and accurate convergent solution to the Laplace equation can be obtained, with less memory and CPU time required, as compared to the results obtained by using the commercial FEM software of either MAXWELL 3D or ANSYS.

In this paper, the thermal characteristic of the GaN HFETs has been analyzed using the hybrid finite element method (FEM). Both the steady and transient state thermal operations are quantitatively studied with the effects of temperature-dependent thermal conductivities of GaN and the substrate materials properly treated. The temperature distribution and the maximum temperatures of the HFETs operated under excitations of continuous-waves (CW) and pulsed-waves (PW) including double exponential shape PW such as electromagnetic pulse (EMP) and ultra-wideband (UWB) signal are studied and compared.

In this letter, an analytic model for real-time flow connections in a Wireless Mobile Internet (WMI) is developed, and then performance measures are derived. Some examples are also presented in order to show the call-blocking ratio and the number of connections admitted into a WMI.

In the design of an active integrated antenna, it is necessary to analyze problems such as unwanted emissions or mutual coupling between elements. In this paper, we clarify the problems in implementing S-parameters for an FDTD analysis. Cubic spline interpolation is suitable for the construction of the S-parameter data. The implementation methods of terminal resistors and vias are examined. The proposed FDTD analysis becomes stable after correcting the discrete time lag in the formation of the incident wave. The validity of the proposed method is verified in its application to the low pass filter and the frequency tunable band pass filter.

Writing/non-writing of composite conducting polymer (polypyrrole/poly(3-hexylthiophene)) have been investigated using composite conducting polymer. Writing has been made in two processes: pretreatment and dropping ethanol. The unipolar signal (10 Vp-p, 10 Hz+5 VDC) has worked as a circuit signal. The conductivity at the path of the composite conducting polymer network has depended on the passed signal. It was confirmed using the Y-type and H-type composite conducting polymer. It has been confirmed that rewriting of composite conducting polymer is possible to develop a memory or a neural network device of conducting polymer.

In this article, we considered the asymptotic expectations of the prediction error and the fitting error of a regression model, in which the component functions are chosen from a finite set of orthogonal functions. Under the least squares estimation, we showed that the asymptotic bias in estimating the prediction error based on the fitting error includes the true number of components, which is essentially unknown in practical applications. On the other hand, under a suitable shrinkage method, we showed that an asymptotically unbiased estimate of the prediction error is given by the fitting error plus a known term except the noise variance.

A simple analytical model based on Delayed Quadratic (DQ) Transfer Function approximation is proposed for estimating waveforms of inductive single-line interconnects in VLSI's. An expression for overshoot voltage is derived by the model within 17% error for the line width less than 10 times the minimum line width and typical input signal. A delay expression is also proposed within 15% for the same condition. The strength of the inductive effect is shown to be expressed by a closed-form expression, A=2(L(CT+0.5C))1/2/(RT(CT+CJ)+RTC+RCT+0.4RC). By using the criteria, a scaling trend of inductive effects in VLSI's is discussed. It is shown that the inductive effect of single-line, minimum-width VLSI interconnect peaks off at 90 nm based on the ITRS predicted parameters.

We give the necessary and sufficient conditions for a one-dimensional discrete-time autonomous binary cellular neural networks to be stable in the case of fixed boundary. The results are complete generalization of our previous one [16] in which the symmetrical connections were assumed. The conditions are compared with some stability conditions so far known.

This paper represents a cycle-based logic simulation method using an LUT cascade emulator, where an LUT cascade consists of multiple-output LUTs (cells) connected in series. The LUT cascade emulator is an architecture that emulates LUT cascades. It has a control part, a memory for logic, and registers. It connects the memory to registers through a programmable interconnection circuit, and evaluates the given circuit stored in the memory. The LUT cascade emulator runs on an ordinary PC. This paper also compares the method with a Levelized Compiled Code (LCC) simulator and a simulator using a Quasi-Reduced Multi-valued Decision Diagram (QRMDD). Our simulator is 3.5 to 10.6 times faster than the LCC, and 1.1 to 3.9 times faster than the one using a QRMDD. The simulation setup time is 2.0 to 9.8 times shorter than the LCC. The necessary amount of memory is 1/1.8 to 1/5.5 of the one using a QRMDD.

This paper proposes a method to determine a single frequency for interconnect RL extraction. Resistance and inductance of interconnects depend on frequency, and hence the extraction frequency strongly affects the modeling accuracy of interconnects. The proposed method determines an extraction frequency based on the transfer characteristic of interconnects. By choosing the frequency where the transfer characteristic becomes maximum, the extracted RL values achieve the accurate modeling of the waveform. Experimental results show that the proposed method provides accurate transition waveforms over various interconnect topologies.

One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In MTCMOS circuit, voltage on virtual ground fluctuates due to a discharge current of a logic cell. This event affects to the cell delay and makes static timing analysis (STA) difficult. In this paper, we propose a delay modeling and static STA methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. This technique enables to calculate the cell delay considering the delay increase by the voltage fluctuation of virtual ground line. Experimental results show that the proposed methodology enables to estimate the cell delay and the critical path delay within 8% errors compared with SPICE simulation.

The purpose of this study is to maintain efficient backup routes for reconstructing overlay trees quickly. In most conventional methods, after a node leaves the trees, its child nodes start searching for the new parents. In this reactive approach, it takes a lot of time to find a new parent. In this paper, we propose a proactive approach to finding a next parent as the backup route node over the overlay tree before the current parent leaves. A proactive approach allows a node to find its new parent node immediately and switch to the backup route node smoothly. In our proposal, the structure of the overlay tree using a redundant degree can decide a backup route node without so much overhead. Simulations demonstrate our proactive approach can recover from node departures 2 times faster than reactive approaches, and can construct overlay trees with lower overheads than another proactive method. Additionally we carried out experiments over actual networks and their results support the effectiveness of our approach. We confirmed that our proposal achieved better streaming quality than conventional approaches.

Digital watermarking techniques were developed for regular raster data such as images or video, but little research addressed irregular vector data, such as the shapes of cartoons or elevation contours. Vector graphic images, such as those in SVG format, are popular on the WWW, and provide the advantage of permitting affine transformations without aliasing. The creation of cartoon images or the acquisition of GIS geometry data involves much work, so the copyright and ownership of vector data must be protected. Common components in vector graphic images are polygonal lines or polylines. This work develops a normal multi-resolution representation of a polygonal line, and embeds a copyright notice or serial number in this representation. Previous studies on polyline watermarking have the non-transparent problems, including self-intersection of line segments. The experimental results demonstrate that the proposed watermarking approach is perceptually transparent, and solves the self-intersection problem. It is also resistant to similarity transformation, traversal reordering, point insertion/deletion and random noise attacks.

Molecular aligned naphthacene thins films were fabricated using vacuum evaporation and the rubbing method. The attenuated total reflection (ATR) and emission light properties from surface plasmon (SP) excitation due to molecular luminescence were investigated for these films. The long axis of the rod-like molecule was estimated to align perpendicular to the rubbing direction. The ATR and emission light properties depended on the molecular orientation.

This paper presents a scheme for accurately detecting the number of incident waves arriving at array antennas. The array antenna and MIMO techniques are developing as 4th generation mobile communication systems and wireless LAN technologies, and the accurate estimation of the propagation environment is becoming more important. This paper emphasizes the accurate detection of the number of incident waves; one of the important characteristics in multidirectional communication. There are some recent papers on accurate detection but they have problems of estimation accuracy or computational cost in severe environment like low SNR, small number of snapshots or waves with close angles. Hence, AIC and MDL methods based on statistics and information theory are still often used. In this paper, we propose an accurate estimation method of the number of arrival signals using the orthogonality of subspaces derived from preliminary estimation of signal subspace. The proposed method accurately estimates the number of signals also in severe environments where AIC and MDL methods can hardly estimate. We evaluate the performance of these methods through some computer simulation and experiments in anechoic chamber.

Recently, the number of multi-homed hosts is getting large, which are equipped with multiple network interfaces to support multiple IP addresses. Although there are several proposals that aim at bandwidth aggregation for multi-homed hosts, few of them support mobility. This paper proposes a new framework called AMS: Aggregate-bandwidth Multi-homing Support. AMS provides functions of not only bandwidth aggregation but also mobility by responding to the changes of the number of connections during communication without the support of underlying infrastructure. To achieve efficient data transmission, AMS introduces a function called address pairs selection to select an optimal combination of addresses of the peer nodes. We implemented AMS in the kernel of NetBSD and evaluated it in our test network, in which dummynet was used to control bandwidth and delay. The measured results showed that AMS achieved ideal bandwidth aggregation in three TCP connections by selecting optimal address pairs.

A compact representation of the Green function is proposed by applying the discrete wavelet concept in the k-domain, which can be used for the acceleration of scattered field calculations in integral equation methods. A mathematical expression of the Green function based on the discrete wavelet concept is derived and its characteristics are discussed.

As VLSI technology advances, delay variations will become more serious. Delay-insensitive asynchronous dual-rail circuits tolerate any delay variation, but their energy consumption is more than double that of the single-rail circuits because signal transitions occur every cycle in all bits regardless of the input bit pattern. However, in functional units, a significant number of input bits may not change from the previous input in many cases. In such a situation, calculation of these bits is not required. Thus, we propose a method, called unflip-bits control, makes use of the above situation, to reduce energy consumption. We evaluate the energy consumption and performance penalty for the method using HSPICE and the verilog-XL simulator, and compare the method with the conventional dual-rail circuit and a synchronous circuit. Our evaluation results reveal that the proposed asynchronous dual-rail circuit has a 12-60% lower energy consumption compared with a conventional asynchronous dual-rail circuit.

Network emulation system constructs a virtual network environment which has the characteristics of controllable and repeatable network conditions. This makes it possible to predict the correctness and performance of proposed new technology before deploying to Internet. In this paper we present a methodology for evaluating the correctness and performance of applications based on the PARNEM, a parallel discrete event network emulator. PARNEM employs a BSP based real-time event scheduling engine, provides flexible interactive mechanism and facilitates legacy network models reuse. PARNEM allows detailed and accurate study of application behavior. Comprehensive case studies covering bottleneck bandwidth measurement and distributed cooperative web caching system demonstrate that network emulation technology opens a wide range of new opportunities for examining the behavior of applications.

Despite the extensive literature on current conveyor-based voltage-mode first-order all-pass filters, no filter circuits have been reported to date that simultaneously achieve all of the advantageous features: (i) the employment of only one current conveyor, (ii) the employment of only one grounded capacitor, (iii) the employment of only one resistor, (iv) no need to impose component choice conditions, and (v) low active and passive sensitivities. In this letter, we describe such a filter structure with all of the above features simultaneously present, without trade-offs. H-Spice simulation results using the TSMC025 process and 1.25 V supply voltages validate the theoretical predictions.