Image registration is an important topic in medical image analysis. It is usually used in 2D mosaics to construct the whole image of a biological specimen or in 3D reconstruction to build up the structure of an examined specimen from a series of microscopic images. Nevertheless, owing to a variety of factors, including microscopic optics, mechanisms, sensors, and manipulation, there may be great differences between the acquired image slices even if they are adjacent. The common differences include the chromatic aberration as well as the geometry discrepancy that is caused by cuts, tears, folds, and deformation. They usually make the registration problem a difficult challenge to achieve. In this paper, we propose an efficient registration method, which consists of a feature-based registration approach based on analytic robust point matching (ARPM) and a refinement procedure of the feature-based Levenberg-Marquardt algorithm (FLM), to automatically reconstruct 3D vessels of the rat brains from a series of microscopic images. The registration algorithm could speedily evaluate the spatial correspondence and geometric transformation between two point sets with different sizes. In addition, to achieve subpixel accuracy, an FLM method is used to refine the registered results. Due to the nonlinear characteristic of FLM method, it converges much faster than most other methods. We evaluate the performance of proposed method by comparing it with well-known thin-plate spline robust point matching (TPS-RPM) algorithm. The results indicate that the ARPM algorithm together with the FLM method is not only a robust but efficient method in image registration.

The logistic map is a chaotic mapping. Although several studies have examined logistic maps over real domains with infinite/finite precisions, there has been little analysis of the logistic map over integers. Focusing on differences between the logistic map over the real domain with infinite precision and the logistic map over integers with finite precision, we herein show the characteristic properties of the logistic map over integers and discuss the sequences generated by the map.

Design-complexity metrics, while measured from the code, have shown to be good predictors of fault-prone object-oriented programs. Some of the most often used metrics are the Chidamber and Kemerer metrics (CK). This paper discusses how to make early predictions of fault-prone object-oriented classes, using a UML approximation of three CK metrics. First, we present a simple approach to approximate Weighted Methods per Class (WMC), Response For Class (RFC) and Coupling Between Objects (CBO) CK metrics using UML collaboration diagrams. Then, we study the application of two data normalization techniques. Such study has a twofold purpose: to decrease the error approximation in measuring the mentioned CK metrics from UML diagrams, and to obtain a more similar data distribution of these metrics among software projects so that better prediction results are obtained when using the same prediction model across different software projects. Finally, we construct three prediction models with the source code of a package of an open source software project (Mylyn from Eclipse), and we test them with several other packages and three different small size software projects, using their UML and code metrics for comparison. The results of our empirical study lead us to conclude that the proposed UML RFC and UML CBO metrics can predict fault-proneness of code almost with the same accuracy as their respective code metrics do. The elimination of outliers and the normalization procedure used were of great utility, not only for enabling our UML metrics to predict fault-proneness of code using a code-based prediction model but also for improving the prediction results of our models across different software packages and projects.

Kernel logistic regression (KLR) is a powerful and flexible classification algorithm, which possesses an ability to provide the confidence of class prediction. However, its training--typically carried out by (quasi-)Newton methods--is rather time-consuming. In this paper, we propose an alternative probabilistic classification algorithm called Least-Squares Probabilistic Classifier (LSPC). KLR models the class-posterior probability by the log-linear combination of kernel functions and its parameters are learned by (regularized) maximum likelihood. In contrast, LSPC employs the linear combination of kernel functions and its parameters are learned by regularized least-squares fitting of the true class-posterior probability. Thanks to this linear regularized least-squares formulation, the solution of LSPC can be computed analytically just by solving a regularized system of linear equations in a class-wise manner. Thus LSPC is computationally very efficient and numerically stable. Through experiments, we show that the computation time of LSPC is faster than that of KLR by two orders of magnitude, with comparable classification accuracy.

Feedback shift registers are basic building blocks for many cryptographic primitives. Due to the insecurities of Linear Feedback Shift Register (LFSR) based systems, the use of Nonlinear Feedback Shift Registers (NFSRs) became more popular. In this work, we study the feedback functions of NFSRs with period 2n. First, we provide two new necessary conditions for feedback functions to be maximum length. Then, we consider NFSRs with k-monomial feedback functions and focus on two extreme cases where k=4 and k=2n-1. We study construction methods for these special cases.

Image sequence registration has attracted increasing attention due to its significance in image processing and computer vision. In this paper, we put forward a new kernel based image registration approach, combining both feature-based and intensity-based methods. The proposed algorithm consists of two steps. The first step utilizes feature points to roughly estimate a motion parameter between successive frames; the second step applies our kernel based idea to align all the frames to the reference frame (typically the first frame). Experimental results using both synthetic and real image sequences demonstrate that our approach can automatically register all the image frames and be robust against illumination change, occlusion and image noise.

This study examines movement-based registration (MBR). In MBR, a mobile station (MS) performs location registration whenever the number of entering cells reaches the specified movement threshold M. MBR is simple and its implementation is quite straightforward. However, it may result in more registrations than other similar schemes. We propose an improved MBR scheme, in which MBR combines with implicit registration (IR), to reduce registration cost. The performance of the proposed scheme is evaluated using a mathematical approach based on the 2-dimensional random walk mobility model in a hexagonal cell configuration. The numerical results for varying circumstances show that the proposed scheme performs better than conventional MBR.

Density ratio estimation has gathered a great deal of attention recently since it can be used for various data processing tasks. In this paper, we consider three methods of density ratio estimation: (A) the numerator and denominator densities are separately estimated and then the ratio of the estimated densities is computed, (B) a logistic regression classifier discriminating denominator samples from numerator samples is learned and then the ratio of the posterior probabilities is computed, and (C) the density ratio function is directly modeled and learned by minimizing the empirical Kullback-Leibler divergence. We first prove that when the numerator and denominator densities are known to be members of the exponential family, (A) is better than (B) and (B) is better than (C). Then we show that once the model assumption is violated, (C) is better than (A) and (B). Thus in practical situations where no exact model is available, (C) would be the most promising approach to density ratio estimation.

The problem of recovering a high-resolution frame from a sequence of low-resolution frames is considered. In general, video frames cannot be related through global parametric transformation due to the arbitrary individual pixel movement between frame pairs. To overcome this problem, we propose to employ region-matching technique for motion estimation with a modified model for frame alignment. To do that, the reference frame is segmented into arbitrary-shaped regions which are further matched with that of the other frames. Then, the frame alignment is accomplished by optimizing the cost function that consists of L1-norm of the difference between the interpolated low-resolution (LR) frames and the simulated LR frames. The experimental results demonstrate that using region matching in motion estimation step with the modified alignment model works better than other motion models such as affine, block matching, and optical flow motion models.

As device feature size decreases, interconnection delay becomes the dominating factor of circuit total delay. Distributed-register architectures can reduce the influence of interconnection delay. They may, however, increase circuit area because they require many local registers. Moreover original distributed-register architectures do not consider control signal delay, which may be the bottleneck in a circuit. In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Our method is based on iterative improvement of scheduling/binding and floorplanning. First, we prepare shared-register groups with global controllers, each of which corresponds to a single functional unit. As iterations proceed, we use local registers and local controllers for functional units on a critical path. Shared-register groups physically located close to each other are merged into a single group. Accordingly, global controllers are merged. Finally, our method obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that the area is decreased by 4.7% while maintaining the performance of the circuit equal with that using original distributed-register architectures.

This paper proposes a new sieving algorithm that employs a bucket sort as a part of a factoring algorithm such as the number field sieve. The sieving step requires an enormous number of memory updates; however, these updates usually cause cache hit misses. The proposed algorithm significantly reduces the number of cache hit misses when the size of the sieving region is roughly less than the square of the cache size, and the memory updates are several times faster than the straightforward implementation according to the PC experiments.

For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. This paper treats the hold constraint in a datapath circuit, and discusses a register assignment in high level synthesis considering delay variations. Our approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path delay compensation (MDC) in this paper. MDC can be done by inserting delay elements mainly in non-critical paths of a functional unit (FU). One of our contributions is to show that the minimization of the number of minimum-path delay compensated FUs is NP-hard in general, and it is in the class P if the number of FUs is a constant. A polynomial time algorithm for the latter is also shown in this paper. In addition, an integer linear programming (ILP) formulation is also presented. The proposed method generates a datapath having (1) robustness against delay variations, which is ensured partly by MDC technique and partly by SRV-based register assignment, and (2) the minimum possible numbers of MDCs and registers.

This paper presents a technique for high-accuracy estimation of image rotation using 1D Phase-Only Correlation (POC). The rotation angle between two images is estimated as follows: (i) compute the amplitude spectra of the given images, (ii) transform the coordinate system of amplitude spectra from Cartesian coordinates to polar coordinates, and (iii) estimate the translational displacement between the polar-mapped amplitude spectra to obtain the rotation angle. While the conventional approach is to employ 2D POC for high-accuracy displacement estimation in (iii), this paper proposes the use of 1D POC with an adaptive line selection scheme. The proposed technique makes possible to improve the accuracy of rotation estimation for low contrast images of artificial objects with regular geometric shapes and to reduce the total computation cost by 50%.

Considering the inaccuracy of image registration, we propose a new regularization restoration algorithm to solve the ill-posed super-resolution (SR) problem. Registration error is used to obtain cross-channel error information caused by inaccurate image registration. The registration error is considered as the noise mean added into the within-channel observation noise which is known as Additive White Gaussian Noise (AWGN). Based on this consideration, two constraints are regulated pixel by pixel within the framework of Miller's regularization. Regularization parameters connect the two constraints to construct a cost function. The regularization parameters are estimated adaptively in each pixel in terms of the registration error and in each observation channel in terms of the AWGN. In the iterative implementation of the proposed algorithm, sub-sampling operation and sampling aliasing in the detector model are dealt with respectively to make the restored HR image approach the original one further. The transpose of the sub-sampling operation is implemented by nearest interpolation. Simulations show that the proposed regularization algorithm can restore HR images with much sharper edges and greater SNR improvement.

Although a lot of works for location management in wireless networks have been reported in the literature, most of the works have been focused on designing per-user-based strategies. This means that they can achieve the performance enhancement only for a certain class of mobile users with a specific range of CMR (call-to-mobility ratio). However, these per-user-based strategies can actually degrade the performance if a user's CMR changes significantly. Therefore, an efficient uniform location management strategy, which can be commonly applied to all mobile users regardless of their CMR, is proposed and analyzed in this paper. The motivation behind the proposed strategy is to exploit the concepts of the two well-known existing strategies: the location caching strategy and the local anchor strategy. That is, the location caching strategy exploits locality in a user's calling pattern, whereas the local anchor strategy exploits locality in a user's mobility pattern. By exploiting these characteristics of both strategies together with the profile management at the HLR (home location register), the proposed strategy can reduce the frequent access to the HLR, and thus effectively results in significant reduction in terms of the total location management cost. The analytical results also demonstrate that the proposed strategy can be uniformly applied to all mobile users, while always maintaining the performance gain over the IS-41 standard regardless of a user's CMR and the network traffic conditions.

A formal approach for specifying and reasoning about earth-friendly logistics management systems is presented. To reduce fossil fuel consumption and carbon dioxide emissions resulting from transport, we must enhance the transport efficiency of trucks, which play an essential role as carriers in modern logistics services. This paper addresses the milk-run approach. It is one of the most effective and popular solutions to this problem, but it makes it be complicated to implement in a logistics management system. We propose a language for specifying the routes of trucks and an order relation between the requirements of routes and the possible routes of trucks. The former is formulated as process calculus and the latter selects suitable trucks according to their routes.

Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation while maintaining the circuit behavior and topology. However, if the minimum feasible clock period is reduced, then the number of registers tends to be increased. In this paper, we propose a gate-level register relocation method that reduces the number of registers while keeping the target clock period. In experiments, the proposed method reduces the number of registers in the practical time in most circuits.

As GML is becoming the de facto standard for geographic data storage, transmission and exchange, more and more geographic data exists in GML format. In applications, GML documents are usually very large in size because they contain a large number of verbose markup tags and a large amount of spatial coordinate data. In order to speedup data transmission and reduce network cost, it is essential to develop effective and efficient GML compression tools. Although GML is a special case of XML, current XML compressors are not effective if directly applied to GML, because these compressors have been designed for general XML data. In this paper, we propose GPress, a compressor for effectively compressing GML documents. To the best of our knowledge, GPress is the first compressor specifically for GML documents compression. GPress exploits the unique characteristics of GML documents to achieve good performance. Extensive experiments over real-world GML documents show that GPress evidently outperforms XMill (one of the best existing XML compressors) in compression ratio, while its compression efficiency is comparable to the existing XML compressors.

As the feature size of VLSI becomes smaller, delay variations become a serious problem in VLSI. In this paper, we propose a novel class of robustness for a datapath against delay variations, which is named structural robustness against delay variation (SRV), and propose sufficient conditions for a datapath to have SRV. A resultant circuit designed under these conditions has a larger timing margin to delay variations than previous designs without sacrificing effective computation time. In addition, under any degree of delay variations, we can always find an available clock frequency for a datapath having SRV property to operate correctly, which could be a preferable characteristic in IP-based design.

The delay time (tdT), power dissipation (PT) and circuit volume of a CMOS register array were minimized. Seven test circuits, each of which had a register array and a single clock tree that generated a pair of complement clock pulses, and a conventional register were fabricated using 90-nm CMOS technology. The register array was constructed with M delay flip-flops (FFs) and the clock tree, which consisted of 2 driver stages. Each driver stage had m inverters, each of which drove M/m FFs where M was fixed at 40 and m varied from 1 to 40. The minimum values of tdT and PT were 0.25 ns and 17.88 µW, respectively, and were both obtained when m was 10. These values were 71.4% and 70.4% of tdT and PT for the conventional register, for which m is 40, respectively. The number of inverters in the clock tree when m was 10 was 21 which was only 25.9% that for the conventional register. The measured results agreed well with SPICE-simulated results. Furthermore, for values of M from 20 to 320, both the minimum tdT and the minimum PT were obtained when m was approximately 1.5 times the square root of M.