This paper presents a new architecture for multiple-input signature analyzers. The proposed signature analyzer with Hδ inputs is designed by parallelizing a GLFSR(δ,m), where δ is the number of input signals and m is the number of stages in the feedback shift register. The GLFSR, developed by Pradhan and Gupta, is a general framework for representing LFSR-based signature analyzers. The parallelization technique described in this paper can be applied to any kind of GLFSR signature analyzer, e. g. , SISRs, MISRs, multiple MISRs and MLFSRs. It is shown that a proposed signature analyzer with Hδ inputs requires less complex hardware than either single GLFSR(Hδ,m)s or a parallel construction of the H original GLFSR(δ,m)s. It is also shown that the proposed signature analyzer, while requiring simpler hardware, has comparable aliasing probability with analyzers using conventional GLFSRs for some CUT error models of the same test response length and test time. The proposed technique would be practical for testing CUTs with a large number of output sequences, since the test circuit occupies a smaller area on the LSI chip than the conventional multiple-input signature analyzers of comparable aliasing probability.

A 167-MHz 1-Mbit CMOS synchronous cache SRAM was developed using 0.40-µm process technology. The floor plan was designed so that the address registers are located in the center of the chip, and high-speed circuits were developed such as the quasi latch (QL) sense amplifier and the one-shot control (OSC) output register. To maintain suitable setup and hold time margins, an equivalent margin (EM) design method was developed. 167-MHz operation was measured at a supply voltage of 2.5 V and an ambient temperature of 75. The same margins 1.1 ns of the setup time and hold time were measured for the specifications of a setup time of 2.0 ns and a hold time of 0.5 ns.

The multiple registration schemes (MRSs) proposed here are classified into 3 cases by combining five registration schemes which are power up registration scheme (PURS), power down registration scheme (PDRS), zone based registration scheme (ZBRS), distance based registration scheme (DBRS), and implicit registration scheme (IRS) as follows: the first is MRS1 which covers PURS, PDRS, and ZBRS; the second is MRS2 which covers PURS, PDRS, and DBRS; the third is MRS3 which covers PURS, PDRS, IRS, and DBRS. The three proposed schemes are compared each other by analyzing their combined signaling traffic of paging and registration with considering various parameters of a mobile station behavior (unencumbered call duration, power up and down rate, velocity, etc.). Also, we derive allowable location areas from which the optimal location area is obtained. Numerical results show that MRS3 yields better performance than ZBRS, DBRS, MRS1, and MRS2 in most cases of a mobile station behavior, and it has an advantage of distributing the load of signaling traffic into every cell, which is important in personal communication system.

In this paper, we evaluated performance of mobile exchange control network. Queueing network model is used for modeling of mobile exchange control network. We developed a call control processing and location registration scenario that has a message exchange function between processors in mobile exchange control network. The network symbols are used the simulation models that are composed of the initialization module, message generation module, message routing module, message processing module, message generation module, HIPC network processing module, output analysis module. As a result of computer simulation, we obtain the processor utilization, the mean queue length, the mean waiting time of control network based on call processing and location registration capacity. The call processing and location registration capacity are referred by the number of call attempts in the mobile exchange and must be satisfied with the quality of service (delay time).

Recently, Yagisawa proposed a public key cryptosystem which is very similar to the modified Lu-Lee cryptosystem. The differences are the set of messages and the decryption. On the other hand, Brickell and Odlyzko showed that the modified Lu-Lee cryptosystem is completely broken in polynomial time. This paper shows that Yagisawa cryptosystem is completely broken in the same way.

An approach to design for testability using register-transfer level (RTL) partial scan selection is described. We define an RTL circuit model which enables efficient description in an electronic system design automation (ESDA) tool and testability analysis which leads to effective partial scan selection for RTL design including data path circuits and control circuits such as state machines. We also introduced a method of partial scan selection at RTL which selects critical registers and state machines based on RTL testability analysis. DFT techniques using gate level testability measures have been studied and concluded that they are not successful in achieving high fault coverage [15]. However, we started this work for the following reasons, 1) In sequential ATPG procedure, more than two memory elements belonging to a functional units such as registers and state machines are often required to be justified at a time. At RTL, state machines and registers are explicitly described and recognized as functional units while gate level memory elements are scattered over the circuit. 2) As discussed in [6], if the circuit is modified so that the test sequence which causes state transition between initial and final states of sequential ATPG can be easily obtained, ATPG results can be also improved. Complex state machines can be identified at RTL. According to the experimental results, our gate level DFT achieves high fault coverage comparable with the previously published most successful DFT methods, and DFT at RTL resulted in higher fault coverage than gate level DFT at much shorter CPU time.

A GTL/LV-CMOS interfaced 1 M bit(32k words 36bits/64k words18bits) BiCMOS cache SRAM is designed within a 5.65 10.54mm2 chip size. The process is 0.4µm BiCMOS with 4 poly-Si layers, 3 Metal layers, and TFT memory cells(2.66 4.94µm2). The late write operation is newly adopted. The late write operation method improvements make the fast access time 6 ns and the shorter cycle time 5 ns.

The synergistic effects obtained by adopting both space diversity reception and adaptive equalization play a very important role in circuit outage reduction. This paper quantitatively analyzes these synergistic effects when dispersive and flat fading occur simultaneously. Analytical results show that the synergistic effects are of the same magnitude as the adaptive equalizer improvement factor when only dispersive fading causes outage. The synergistic effects gradually disappear when noise is the predominant cause of outage.

In this paper, we propose a register file with data bypassing function. This register file bypasses data using data bypassing units instead of functional units when actual operation in functional units such as ALU is unnecessary. Applying this method to a general purpose microprocessor with benchmark programs, we demonstrate 50% power consumption reduction in functional units. Though length of bus lines increases a little due to an additional hardware in register file, as buses are not driven when data is bypassed, power consumption in bus lines is also reduced by 40% compared with the conventional architecture.

The influence of cochannel, adjacent channel and intermodulation constraints on the capacity of the frequency band in the dynamic channel allocation problem is estimated. Algorithms including a backtracking phase with partial reassignment of currently assigned requirements are proposed. Numerical examples show a strong possibility of a 20% capacity improvement compared to the conventional strategies.

In this paper, we develop parallel scrambling techniques for the distributed sample scrambling (DSS), which are directly applicable to the bit- and multibit-interleaved multiplexing environments. We first consider how to realize PSRGs, parallel samplings and parallel corrections for the multibit-parallel DSS (MPDSS), which are the fundamental problems in realizing the MPDSS scramblers and descramblers. The results are summarized in three sets of theorems, and a corollary is attached to each theorem to specifically handle the case of the parallel DSS (PDSS). The theorems and corollaries are supported by examples that demonstrate the relevant MPDSS scramblers and descramblers.

A 3.3 V single power-supply 64 Mb flash memory with a DBL programming scheme has been developed and fabricated with 0.4 µm CMOS technology. 50 ns access time and 256 b erase/programming unit-capacity have been achieved by using hierarchical word- and bit-line structures and DBL programming scheme. Furthermore in order to lower operating voltage the HiCR cell is used. The chip size is 19.3 mm13.3 mm.

A multiple instruction stream-multiple data stream (MIMD) computer is a parallel computer consisting of a large number of identical processing elements. The essential feature that distinguishes one MIMD computer family from another is the interconnection network. In this paper, we are concerned with a representative type of interconnection networks: the hypercube connected network. A family of regular graphs is presented as a possible candidate for the implementation of a distributed system and for fault-tolerant architectures. The symmetry of graphs makes it possible to determine message routing by using a simple distributed algorithm. A candidate having the same property is the hypercube connected network. Arbitrary data permutations are generally accomplished by sorting. For certain classes of permutations, however, this is, for many frequently used permutations in parallel processing such as bit reversal, bit shuffle, bit complement, matrix transpose, butterfly permutations used in FFT algorithms, and segment shuffles, there exist algorithms that are more efficient than the best sorting algorithm. One such class is the bit permute complement (BPC) class of permutations. In this paper, we, first, develop an algorithm to realize an arbitrary BPC permutation in hypercube connected networks. The developed algorithm in hypercube connected networks requires only 1 token memory register in each node. We next evaluate the ability to realize BPC permutations in these networks of an arbitrary size by estimating the number of required routing steps.

In order to shorten the time-to-market, Application-Specific Integrated Circuits (ASIC's) are designed from a library of pre-defined layout implementations for register-transfer modules such as multipliers, adders, RAM, ROM, etc. Current approaches to selecting the implementations from the library usually deal with their timing-area estimates and do not consider delay of the intermodule wiring. However, as sub-micron design rules are utilized for IC fabrication, wiring delay becomes comparable to the functional unit delay and can not longer be ignored even in register-transfer synthesis. In this paper we propose an algorithm that combines module selection with Performance-Driven module placement and reduces an impact of wiring on sub-micron ASIC performance. The algorithm not only efficiently exploits multiple module realizations in the design library, but also finds the module placement which minimizes wiring delay. Experimental results on several benchmarks show that considering both module and wiring issues, more than 30% reduction of the total circuit delay can be achieved.

It is shown that a self–recurrent fuzzy inference can cause chaotic responses at least three membership functions, if the inference rules are set to represent nonlinear relations such as pie–kneading transformation. This system has single input and single output both with crisp values, in which membership functions is taken to be triangular. Extensions to infinite memberships are proposed, so as to reproduce the continuum case of one–dimensional logistic map f(x)=Ax(1–x). And bifurcation diagrams are calculated for number N of memberships of 3, 5, 9 and 17. It is found from bifurcation diagrams that different periodic states coexist at the same bifurcation parameter for N9. This indicates multistability necessarily accompanied with hysteresis effects. Therefore, it is concluded that the final states are not uniquely determined by fuzzy inferences with sufficiently large number of memberships.

A multiple-registered architecture is described for 180 MHz 16 Mbit synchronous DRAM. The proposed architecture realizes a flexible control of critical timings such as I/O line busy time and achieves an operation at 180 MHz clock rate with area penalty of only 5.4% over the conventional DRAM.

In this paper, the fundamental characteristics of tactile recognition by electrical stimulus in order to develop a vision substitution system were described. The electrical stimulus pulse or DC voltage was applied at a touch board, and a conducting band which was connected to the ground level was fastened around a root of finger. First of all, the resistance of finger by the DC voltage was measured and the equivalent circuit of a finger was estimated. It was found that the most of resistance of this mechanism was concentrated at the contact of tip of finger and its value reached to MΩ order. And this resistance widely varied by the contact condition. The resistance of finger itself was relatively low and the contact resistance of band connectoin was about 30 kΩ. Total stray capacitance was about 26-62 nF, which was calculated by our experiments. Secondly, the minimum recognition voltage to applied stimulus pulse was measured by changing frequency, duty-ratio and voltage of pulse. It was found that the most sensitive pulse was in situation of that the frequency range was within from 60 Hz to 300 Hz, the duty-ratio of 20%, and the minimum sensitive voltage was about 13V. Lastly, this electrical stimulus pulse was applied to the touch Braille board. A touch Braille board was controlled by a computer (PC8801). In this system, an input letter from keyboard is translated to Braille code data by a computer automatically, which express the letter by the 6 points for the brind. And a Braille data is output at a touch board. By touching on the contact point of the touch board, a person can recognize Braille points by electrical stimulus. It was found that the Braille recognition by electrical stimulus pulse was available as same as it could be done by raised points.

We propose an advanced hyper parallel testing method which improves the line-mode test method by adding data inversion registers which we call the Advanced Line-mode Test (ALT). This testing method has the same testing capability as the conventional bit-by-bit and multi-bit test method (MBT), because it enables the application of a high sensitive and practical test patterns under the hyper parallel condition. The testing time for fixed data patterns are reduced by 1/1900 (all-0/1, checker board, and etc.). Moreover, the ALT can be applicable to the continuous patterns (march, walking, and etc.). The ALT improved from the line-mode test with registers and comparators (LTR) is able to applicable to the most test patterns and to reduce the testing time remarkably, and is suitable for the ULSI memories.

This paper presents a method for verifying safety property of a communication protocol modeled as two extended communicating finite-state machines with two unbounded FIFO channels connecting them. In this method, four types of atomic formulae specifying a condition on a machine and a condition on a sequence of messages in a channel are introduced. A human verifier describes a logical formula which expresses conditions expected to be satisfied by all reachable global states, and a verification system proves that the formula is indeed satisfied by such states (i.e. the formula is an invariant) by induction. If the invariant is never satisfied in any unsafe state, it can be concluded that the protocol it safe. To show the effectiveness of this method, a sample protocol extracted from the data transfer phase of the OSI session protocol was verified by using the verification system.

In this paper, a construction of de Bruijn sequences using maximum length linear sequences is considered. The construction is based on the well-known cross-join (CJ) method: Maximum length linear sequences are used to produce de Bruijn sequences by the CJ process. Properties of the CJ paris in the maximum length linear sequences are investigated. It is conjectured that the number of CJ pairs in a maximum length linear sequence is given by (22n-3+1)/3-2n-2, where n2 is the length of the linear feedback shift register with the sequence. The CJ paris for some special cases are obtained. An algorithm for finding CJ pairs is described and a method of implementation is discussed briefly.