Logistic regression is a powerful machine learning tool to classify data. When dealing with sensitive or private data, cares are necessary. In this paper, we propose a secure system for privacy-protecting both the training and predicting data in logistic regression via homomorphic encryption. Perhaps surprisingly, despite the non-polynomial tasks of training and predicting in logistic regression, we show that only additively homomorphic encryption is needed to build our system. Indeed, we instantiate our system with Paillier, LWE-based, and ring-LWE-based encryption schemes, highlighting the merits and demerits of each instantiation. Besides examining the costs of computation and communication, we carefully test our system over real datasets to demonstrate its utility.

In order to tackle a process-variation problem, we can define several scenarios, each of which corresponds to a particular LSI behavior, such as a typical-case scenario and a worst-case scenario. By designing a single LSI chip which realizes multiple scenarios simultaneously, we can have a process-variation-tolerant LSI chip. In this paper, we propose a multi-scenario high-level synthesis algorithm for variation-tolerant floorplan-driven design targeting new distributed-register architectures, called HDR architectures. We assume two scenarios, a typical-case scenario and a worst-case scenario, and realize them onto a single chip. We first schedule/bind each of the scenarios independently. After that, we commonize the scheduling/binding results for the typical-case and worst-case scenarios and thus generate a commonized area-minimized floorplan result. At that time, we can explicitly take into account interconnection delays by using distributed-register architectures. Experimental results show that our algorithm reduces the latency of the typical-case scenario by up to 50% without increasing the latency of the worst-case scenario, compared with several existing methods.

A 10-bit 20-MS/s asynchronous SAR ADC with a meta-stability detector using replica comparators is proposed. The proposed SAR ADC with the area of 0.093mm2 is implemented using a 130-nm CMOS process with a 1.2-V supply. The measured peak ENOBs for the full rail-to-rail differential input signal is 9.6bits.

This paper presents a method for registering retinal images. Retinal image registration is crucial for the diagnoses and treatments of various eye conditions and diseases such as myopia and diabetic retinopathy. Retinal image registration is challenging because the images have non-uniform contrasts and intensity distributions, as well as having large homogeneous non-vascular regions. This paper provides a new retinal image registration method by effectively combining expectation maximization principal component analysis based mutual information (EMPCA-MI) with salient features. Experimental results show that our method is more efficient and robust than the conventional EMPCA-MI method.

In our previous work [12], [13], we introduced generalized feed-forward shift registers (GF2SR, for short) to apply them to secure and testable scan design. In this paper, we introduce another class of generalized shift registers called generalized feedback shift registers (GFSR, for short), and consider the properties of GFSR that are useful for secure scan design. We present how to control/observe GFSR to guarantee scan-in and scan-out operations that can be overlapped in the same way as the conventional scan testing. Testability and security of scan design using GFSR are considered. The cardinality of each class is clarified. We also present how to design strongly secure GFSR as well as GF2SR considered in [13].

Out-of-order superscalar processors rename register numbers to remove false dependencies between instructions. A renaming logic for register renaming is a high-cost module in a superscalar processor, and it consumes considerable energy. A renamed trace cache (RTC) was proposed for reducing the energy consumption of a renaming logic. An RTC caches and reuses renamed operands, and thus, register renaming can be omitted on RTC hits. However, conventional RTCs suffer from several performance, energy consumption, and hardware overhead problems. We propose a semi-global renamed trace cache (SGRTC) that caches only renamed operands that are short distance from producers outside traces, and solves the problems of conventional RTCs. Evaluation results show that SGRTC achieves 64% lower energy consumption for renaming with a 0.2% performance overhead as compared to a conventional processor.

Quantum computer simulators play an important role when we evaluate quantum algorithms. Quantum computation can be regarded as parallel computation in some sense, and thus, it is suitable to implement a simulator on hardware that can process a lot of operations in parallel. In this paper, we propose a hardware quantum computer simulator. The proposed simulator is based on the register reordering method that shifts and swaps registers containing probability amplitudes so that the probability amplitudes of target basis states can be quickly selected. This reduces the number of large multiplexers and improves clock frequency. We implement the simulator on an FPGA. Experiments show that the proposed simulator has scalability in terms of the number of quantum bits, and can simulate quantum algorithms faster than software simulators.

The Process Virtual Machine (VM) is typical software that runs applications inside operating systems. Its purpose is to provide a platform-independent programming environment that abstracts away details of the underlying hardware, operating system and allows bytecodes (portable code) to be executed in the same way on any other platforms. The Process VMs are implemented using an interpreter to interpret bytecode instead of direct execution of host machine codes. Thus, the bytecode execution is slower than those of the compiled programming language execution. Several techniques including our previous paper, the “Fetch/Decode Hardware Extension”, have been proposed to speed up the interpretation of Process VMs. In this paper, we propose an additional methodology, the “Hardware Extension with Hybrid Execution” to further enhance the performance of Process VMs interpretation and focus on Register-based model. This new technique provides an additional decoder which can classify bytecodes into either simple or complex instructions. With “Hybrid Execution”, the simple instruction will be directly executed on hardware of native processor. The complex instruction will be emulated by the “extra optimized bytecode software handler” of native processor. In order to eliminate the overheads of retrieving and storing operand on memory, we utilize the physical registers instead of (low address) virtual registers. Moreover, the combination of 3 techniques: Delay scheduling, Mode predictor HW and Branch/goto controller can eliminate all of the switching mode overheads between native mode and bytecode mode. The experimental results show the improvements of execution speed on the Arithmetic instructions, loop & conditional instructions and method invocation & return instructions can be achieved up to 16.9x, 16.1x and 3.1x respectively. The approximate size of the proposed hardware extension is 0.04mm2 (or equivalent to 14.81k gates) and consumes an additional power of only 0.24mW. The stated results are obtained from logic synthesis using the TSMC 90nm technology @ 200MHz.

In this paper, we consider the Reed-Solomon codes over Fqm with evaluations in a subfield Fq. By the “virtual extension”, we can embed these codes into homogeneous interleaved Reed-Solomon codes. Based on this property and the collaborative decoding algorithm, a new probabilistic decoding algorithm that can correct errors up to $rac{m}{m+1}(n-k)$ for these codes is proposed. We show that whether the new decoding algorithm fails or not is only dependent on the error. We also give an upper bound on the failure probability of the new decoding algorithm for the case s=2. The new decoding algorithm has some advantages over some known decoding algorithms.

A high energy-efficiency and area-reduction switching scheme for a low-power successive approximation register (SAR) analog-to-digital converter (ADC) is presented. Based on the sequence initialization, monotonic capacitor switching procedure and multiple reference voltages, the average switching energy and total capacitance of the proposed scheme are reduced by 99.4% and 87.5% respectively, compared to the conventional architecture.

In our previous work [12], [13], we introduced generalized feed-forward shift registers (GF2SR, for short) to apply them to secure and testable scan design, where we considered the security problem from the viewpoint of the complexity of identifying the structure of GF2SRs. Although the proposed scan design is secure in the sense that the structure of a GF2SR cannot be identified only from the primary input/output relation, it may not be secure if part of the contents of the circuit leak out. In this paper, we introduce a more secure concept called strong security such that no internal state of strongly secure circuits leaks out, and present how to design such strongly secure GF2SRs.

With recent developments in machine learning technology, the predictions by systems incorporating machine learning can now have a significant impact on the lives and activities of individuals. In some cases, predictions made by machine learning can result unexpectedly in unfair treatments to individuals. For example, if the results are highly dependent on personal attributes, such as gender or ethnicity, hiring decisions might be discriminatory. This paper investigates the neutralization of a probabilistic model with respect to another probabilistic model, referred to as a viewpoint. We present a novel definition of neutrality for probabilistic models, η-neutrality, and introduce a systematic method that uses the maximum likelihood estimation to enforce the neutrality of a prediction model. Our method can be applied to various machine learning algorithms, as demonstrated by η-neutral logistic regression and η-neutral linear regression.

Recently ICT has been improved rapidly, and it is likely to make a contribution to effective disaster response. However, ICT is not utilized effectively in disaster response because the environment for ICT management is not considered enough. In this paper, we retrieve lessons learned from actual response at the past disasters in Japan, and introduce them following disaster response process model based on human psychological manner. In another point, we suggest significance of Common Operational Picture with spatial information following advanced case study in the United States of America, and identify two essential issues for effective information and technology management. One is information status, such as statics or dynamic information. The other one is five elements for ICT management in disaster response: Governance, Standard Operating Procedures, Technology, Training and Exercise and Use.

Track mis-registration (TMR) is one of the major problems in high-density magnetic recording systems such as bit-patterned media recording (BPMR). In general, TMR results from the misalignment between the center of the read head and that of the main track, which can deteriorate the system performance. Although TMR can be handled by a servo system, this paper proposes a novel method to alleviate the TMR effect, based on the readback signal. Specifically, the readback signal is directly used to estimate a TMR level and is then further processed by the suitable target and equalizer designed for such a TMR level. Simulation results indicate that the proposed method can sufficiently estimate the TMR level and then helps improve the system performance if compared to the conventional receiver that does not employ a TMR mitigation method, especially when an areal density is high and/or a TMR level is large.

This work presents a novel counter-based randomization method for use in a flying-adder frequency synthesizer with a cost-effective structure that can replace the fractional accumulator. The proposed technique involves a counter, a comparator and a modified linear feedback shift register. The power consumption and speed bottleneck of the conventional flying-adder are significantly reduced. The modified linear shift feedback register is used as a pseudo random data generator, suppressing the spurious tones arise from the periodic carry sequences that is generated by the fractional accumulator. Furthermore, the proposed counter-based randomization method greatly reduces the large memory size that is required by the conventional approach to carry randomization. A test chip for the proposed counter-based randomization method is fabricated in the TSMC 0.18,$mu $m 1P6M CMOS process, with the core area of 0.093,mm$^{mathrm{2}}$. The output frequency had a range of 43.4,MHz, extasciitilde 225.8,MHz at 1.8,V with peak-to-peak jitter (Pk-Pk) jitter 139.2,ps at 225.8,MHz. Power consumption is 2.8,mW @ 225.8,MHz with 1.8 supply voltage.

A renal biopsy is a procedure to get a small piece of kidney for microscopic examination. With the development of tissue sectioning and medical imaging techniques, microscope renal biopsy image sequences are consequently obtained for computer-aided diagnosis. This paper proposes a new context-based segmentation algorithm for acquired image sequence, in which an improved genetic algorithm (GA) patching method is developed to segment different size target. To guarantee the correctness of first image segmentation and facilitate the use of context information, a boundary fusion operation and a simplified scale-invariant feature transform (SIFT)-based registration are presented respectively. The experimental results show the proposed segmentation algorithm is effective and accurate for renal biopsy image sequence.

People expose their personal information on social network services (SNSs). This paper warns of the dangers of this practice by way of an example. We show that the residence registration numbers (RRNs) of many Koreans, which are very important and confidential personal information analogous to social security numbers in the United States, can be estimated solely from the information that they have made open to the public. In our study, we utilized machine learning algorithms to infer information that was then used to extract a part of the RRNs. Consequently, we were able to extract 45.5% of SNS users' RRNs using a machine learning algorithm and brute-force search that did not consume exorbitant amounts of resources.

When ultra-high-frequency (UHF) method is applied in partial discharge (PD) detection for GIS, the propagation process and rules of electromagnetic (EM) wave need to be understood clearly for conducting diagnosis and assessment about the real insulation status. The preceding researches are mainly concerning about the radial component of the UHF signal, but the propagation of the signal components in axial and radial directions and that perpendicular to the radial direction of the GIS tank are rarely considered. So in this paper, for a 252,kV GIS with T-shaped structure (TS), the propagation and attenuation of PD-induced EM wave in different circumferential angles and directions are investigated profoundly in time and frequency domain based on Finite Difference Time Domain (FDTD) method. The attenuation rules of the peak to peak value (Vpp) and cumulative energy are concluded. By comparing the results of straight branch and T branch, the influence of T-shaped structure over the propagation of different signal components are summarized. Moreover, the new circumferential and axial location methods proposed in the previous work are verified to be still applicable. This paper discusses the propagation mechanism of UHF signal in T-shaped tank, which provides some referential significance towards the utilization of UHF technique and better implementation of PD detection.

For the direct measurement of very fast transient current (VFTC) due to switch operation in gas insulated switchgear (GIS), usually it will interfere the original operation or change the structure of switch. In this paper a method for calculation of transient current caused by the disconnect operation in GIS by the inverse operation of the electromagnetic (EM) near field is presented. A GIS is modeled by the finite integration technique (FIT), and all the media between the excitation source and the observation position are considered as a black box whose input is VFTC and output is EM field. A coefficient matrix is established to reflect the connection between the input and output in frequency domain, and the VFTC in frequency domain will be the result of multiplying the inverse matrix by the measurement result minus the EM field caused by transient grounding potential rise (TGPR) or transient enclosure voltage (TEV) in the observation position. Finally the time domain form of VFTC can be obtained by the interpolation and IFFT. Comparison between the result and simulation shows the validation of this method.

Registration consistency (RC) stands out as a widely-used automatic measure from existing image registration evaluation measures. However the original RC neglects the influence brought by the image intensity variation, leading to several problems. This letter proposes a rectified registration consistency, which takes both image intensity variation and geometrical transformation into consideration. Therefore the geometrical transformation is evaluated more by decreasing the influence of intensity variation. Experiments on real image pairs demonstrated the superiority of the proposed measure over the original RC.