A Si single electron transistor (SET) was fabricated by converting a one-dimensional Si wire on a SIMOX substrate into a small Si island with a tunneling barrier at each end by means of pattern-dependent oxidation. Since the size of the Si island was as small as around 10 nm owing to this novel technique, the total capacitance of the SET was reduced to a value on the order of 1 aF, which guarantees the conductance oscillation of the SET even at room temperature. Furthermore, a linear relation between the designed wire length and the gate capacitance of SETs was obtained, which clearly indicates that the single island was actually formed in the middle of the one dimensional Si wire. These results were achieved owing to the highly reproducible fabrication process based on pattern dependent oxidation of SIMOX-Si layers. In addition, the fluctuation of the electrical characteristics of the SETs Was studied in relation to the wire size fluctuations. It was found that the fluctuatian is caused predominantly by the roughness of the sidewall surface of the resist pattern.

RCS fluctuation of targets such as ships can be reduced by the high-resolution radar. The high-resolution radar resolves the total radar echo into several parts which do not interfere each other. The reduction of interference gives stable target RCS. A simple model of the RCS fluctuation reduction is presented. Typical data for ships taken by an experimental radar which has range resolution about 0.75 m, are also shown. The analysis results show that the RCS fluctuation reduction agree with the simple model well.

This work deals with thermal-noise modeling for silicon vertical bipolar junction transistors (BJTs) and relevant integrated circuits (ICs) operating at low currents. The two-junction BJT compact model is consistently derived from the thermal-noise generalization of the Shockley semiconductor equations developed in work which treats thermal noise as the noise associated with carrier velocity fluctuations. This model describes BJT with the Itô non-linear stochastic-differential-equation (SDE) system and is suitable for large-signal large-fluctuation analysis. It is shown that thermal noise in silicon p-n-junction diode contributes to "microplasma" noise. The above model opens way for a consistent-modeling-based design/optimization of bipolar device noise performance with the help of theory of Itô's SDEs.

This paper proposes a fully self-timing data-bus (FSD) architecture which includes a dual data-bus driven by the read-out data itself and a complementary output differential (COD) amplifier. The proposed COD amplifier achieves a high voltage gain and a high speed data transfer with low power consumption. The read-out data is transmitted from the COD amplifier to the output terminal without the timing control caused by the fluctuation of the device parameters. Therefore the proposed FSD architecture eliminates the timing delay and achieves a timing-free data transfer even in DRAMs with a small signal level at the sense amplifier and the data line. Applying this architecture to a 64-Mb DRAM, a fast column address access time of 16 ns and a RAS access time of 32 ns have been achieved.

This paper proposes a methodology for fine evaluation of the uncertain behaviors of systems affected by any fluctuation of internal structures and internal parameters, by the use of a new concept on the fuzzy mapping. For a uniformly convex real Banach space X and Y, a fuzzy mapping G is introduced as the operator by which we can define a bounded closed compact fuzzy set G(x,y) for any (x,y)∈X×Y. An original system is represented by a completely continuous operator f defined on X, for instance, in a form xλ(f(x)) by a continuous operator λ: YX. The nondeterministic fluctuations induced into the original system are represented by a generalized form of the fuzzy mapping equation xGβ (x,f(x)) {ζX|µG(x,f(x))(ζ)β}, in order to give a fine evaluation of the solutions with respect to an arbitrarily–specified β–level. By establishing a useful fixed point theorem, the existence and evaluation problems of the "β–level-likely" solutions are discussed for this fuzzy mapping equaion. The theory developed here for the fluctuation problems is applied to the fine estimation of not only the uncertain behaviors of system–fluctuations but also the validity of system–models and -simulations with uncertain properties.

The magnitude of low frequency noise is studied in a Nb-(nanoconstrictions)-NbN system with adjustable current-voltage characteristics. We find that the magnitude of low frequency noise decreases sharply with increasing the subgap conductivity of the device. We suggest a qualitative explanation of this observation in terms of gradual build up of the nanoconstriction region by field assisted growth. The decrease of low frequency noise is related to the "cleanliness" of the system as measured by the amount of Andreev reflection-related conductivity. The scaling of the magnitude of low frequency noise with device resistance is also discussed.

Material representations and algorithms are presented for simulation of nanometer lithography. Organic polymer resists are modeled as collections of overlapping spheres, with each sphere representing a polymer chain. Exposure and post-exposure bake steps are modeled at the nanometer scale for both positive and negative resists. The development algorithm is based on the Poisson removal probability for each sphere in contact with developer. The Poisson removal rate for a given sphere is derived from a mass balance relationship with a macroscopic development rate model. Simulations of electron beam lithography with (poly) methyl methacrylate and Shipley SAL-601 reveal edge roughness standard deviations from 2 to 3 nm, leading to linewidth peak-to-peak 3σ variation of 15 to 22 nm. Typical simulations require about 2 MBytes and under 5 minutes on a Sun Sparc 10/41 engineering workstation.

In the direct product space of a complete metric linear space X and its related space Y, a fuzzy mapping G is introduced as an operator by which we can define a projective fuzzy set G(x,y) for any xX and yY. An original system is represented by a completely continuous operator f(x)Y, e.g., in the form x=λ(f(x)), (λ is a linear operator), and a nondeterministic or fuzzy fluctuation induced into the original system is represented by a generalized form of system equation xβG(x,f(x)). By establishing a new fixed point theorem for the fuzzy mapping G, the existence and evaluation problems of solution are discussed for this generalized equation. The analysis developed here for the fluctuation problem goes beyond the scope of the perturbation theory.

This paper describes the higher-order moment analysis of superposed Markov jumping processes. A superposed Markov jumping process is defined as a linear superposition of a finite number of piecewise constant real valued stochastic process whose value changes are associated with state transitions in an underlying descrete state continuous time Markov process. Some phenomena are modeled well by the process such as membrane current fluctuations observed at bio-membranes or load fluctuations in electrical power systems. Theoretical formula of the moment function of any order k is derived and the parameter estimation problem utilizing higher-order moment functions is discussed. A new method of estimating the kinetic parameters of membrane current fluctuations is proposed as a possible application.

The composition of CMOS control circuit and Vertical-Double-Diffused-MOS (VDMOS) power device on a single chip by using Silicon-On-Insulator (SOI) structure is formulated. Because all the MOS transistors in the CMOS control circuit are not isolated by the trenches, the interference phenomenon between SOI and the substrate is studied. Latch-up is detected thus, the construction of a mechanism to prevent latch-up is also studied. To evaluate the SOI CMOS characteristics the effects of voltage fluctuation on the substrate is analized. The latch-up mechanism is also analized by transient device simulation. As a result of this study a guideline for the immunity of latch-up is established, the features of the mechanism are as follows. First, the latch-up trigger is the charging current of the condenser composed of the oxide layer in the SOI structure. Second, latch-up is normally caused by positive feedback between the parasitic PNP-transistor and the parasitic NPN-transistor. However, in this case, electron diffusion toward the P-well is dominant after the parasitic PNP-transistor falls into high level injection. This feature is different from the conventional mechanism. The high level injection is caused by carrier accumulation in the N- region. Considering the above, it is necessary to; (1) reduce the charging current of the condenser, (2) reduce the parasitic resistance in the N- region of SOI, and (3) reduce the carrier accumulation in SOI for immunity from latch-up.