This paper proposes a dual-polarized metasurface that utilizes multi-layer ceramic capacitors (MLCCs) for radar cross-section (RCS) reduction in the 28GHz band of the quasi-millimeter band. MLCCs are very small in size; therefore, miniaturization of the unit cell structure of the metamaterial can be expected, and the MLCCs can be periodically loaded onto a narrow object. First, the MLCC structure was modeled as a basic structure, and the effective permeability of the MLCC was determined to investigate the influence of the arrangement direction on MLCC interaction. Next, the unit cell structure of the dual-polarized metasurface was designed for an MLCC set on a dielectric substrate. By analyzing the infinite periodic structure and finite structure, the monostatic reduction characteristics, oblique incidence characteristics, and dual-polarization characteristics of the proposed metasurface were evaluated. In the case of the MLCCs arranged in the same direction, the monostatic RCS reduction was approximately 30dB at 29.8GHz, and decreased when the MLCCs were arranged in a checkerboard pattern. The monostatic RCS reductions for the 5 × 5, 10 × 10, and 20 × 20 divisions were roughly the same, i.e., 10.8, 9.9, and 10.3dB, respectively. Additionally, to validate the simulated results, the proposed dual-polarized metasurface was fabricated and measured. The measured results were found to approximately agree with the simulated results, confirming that the RCS can be reduced for dual-polarization operation.

In this study, the effect of atomically flat Si(100) surface on Hf-based Metal-Oxide-Nitride-Oxide-Silicon (MONOS) structure was investigated. After the atomically flat Si(100) surface formation by annealing at 1050/60min in Ar/4%H2 ambient, HfO2(O)/HfN1.0(N)/HfO2(O) structure with thickness of 10/3/2nm, respectively, was in-situ deposited by electron cyclotron resonance (ECR) plasma sputtering. The memory window (MW) of Al/HfO2/HfN1.0/HfO2/p-Si(100) diodes was increased from 1.0V to 2.5V by flattening of Si(100) surface. The program and erase (P/E) voltage/time were set as 10V/5s and -8V/5s, respectively. Furthermore, it was found that the gate current density after the 103P/E cycles was decreased one order of magnitude by flattening of Si(100) surface in Ar/4.0%H2 ambient.

We demonstrate on the basis of ab initio calculations that metal-oxide-nitride-oxide-semiconductor (MONOS) memory is one of the most promising future high-density archive memories. We find that O related defects in a MONOS memory cause irreversible structural changes to the SiO2/Si3N4 interface at the atomistic level during program/erase (P/E) cycles. Carrier injection during the programming operation makes the structure energetically very stable, because all the O atoms in this structure take on three-fold-coordination. The estimated lifespan of the programmed state is of the order of a thousand years.

In order to reduce PtSi Schottky barrier height (SBH) for electron, we investigated modulation of PtSi work function by alloying with low work function metal, such as Hf (3.9 eV) and Yb (2.7 eV). Pt (10-20 nm)/Hf, Yb (0-10 nm)/n-Si(100) stacked structures were in-situ deposited at room temperature by RF magnetron sputtering method. In case of PtxHf1 - xSi formed at 400/60 min annealing in N2, SBH for electron was reduced from 0.85 eV to 0.53 eV with Hf thickness without increase of sheet resistance. Yb incorporation also affected the SBH modulation, however, the sheet resistance increased with increase of Yb thickness.

Due to the aggressive scaling of non-volatile memories, “charge-trap memories” such as MONOS-type memories become one of the most important targets. One of the merits of such MONOS-type memories is that they can trap charges inside atomic-scale defect sites in SiN layers. At the same time, however, charge traps with atomistic scale tend to induce additional large structural changes. Hydrogen has attracted a great attention as an important heteroatom in MONOS-type memories. We theoretically investigate the basic characteristics of hydrogen-defects in SiN layer in MONOS-type memories on the basis of the first-principles calculations. We find that SiN structures with a hydrogen impurity tend to reveal reversible structural change during program/erase operation.

A 2-bit operational metal/silicon-oxide-nitride-oxide-silicon (MONOS/SONOS) nonvolatile memory using an asymmetric double-gate (ASDG) MOSFET was studied to double flash memory density. The 2-bit programming and erasing was performed by Fowler-Nordheim (FN) tunneling in a NAND array architecture using individually controlled gates. A threshold voltage shift of programmed states for the 2-bit operation was investigated with the aid of a SILVACO® simulator in both sides of the gate by changing gate workfunctions and tunneling oxide thicknesses. In this paper, the scalability of the device down to 30 nm was demonstrated by numerical simulation. Additionally, guidelines of the 2-bit ASDG nonvolatile memory (NVM) structure and operational conditions were proposed for "program," "read," and "erase."

Target reconstruction algorithm from its monostatic radar cross section (RCS) has been proposed for polygonal cylinders with curved surfaces. This algorithm is based on our previous finding that the main contribution to the back scattering is due to edge diffracted fields excited at a facet of nearly specular reflection direction. Dimension of this constitutive facet of the target is estimated from the local maxima and its lobe width in the angular RCS variation. Half and quarter circular cylinders are used as canonical scattering objects, and their measured and numerically simulated monostatic RCS values have been studied extensively to find scattering pattern characteristic difference between flat and circularly curved surfaces. Thus estimated constitutive facets are connected in order, and this procedure will be continued until the distance between the first and the final edges would be minimized. Our algorithm has been tested for other targets, and it is found that it works well for predicting metal convex targets with flat and curved facets.

This paper presents a study on acoustic modeling for speech recognition of predominantly monosyllabic languages. Various speech units used in speech recognition systems have been investigated. To evaluate the effectiveness of these acoustic models, the Thai language is selected, since it is a predominantly monosyllabic language and has a complex vowel system. Several experiments have been carried out to find the proper speech unit that can accurately create acoustic model and give a higher recognition rate. Results of recognition rates under different acoustic models are given and compared. In addition, this paper proposes a new speech unit for speech recognition, namely onset-rhyme unit. Two models are proposed-the Phonotactic Onset-Rhyme Model (PORM) and the Contextual Onset-Rhyme Model (CORM). The models comprise a pair of onset and rhyme units, which makes up a syllable. An onset comprises an initial consonant and its transition towards the following vowel. Together with the onset, the rhyme consists of a steady vowel segment and a final consonant. Experimental results show that the onset-rhyme model improves on the efficiency of other speech units. The onset-rhyme model improves on the accuracy of the inter-syllable triphone model by nearly 9.3% and of the context-dependent Initial-Final model by nearly 4.7% for the speaker-dependent systems using only an acoustic model, and 5.6% and 4.5% for the speaker-dependent systems using both acoustic and language model respectively. The results show that the onset-rhyme models attain a high recognition rate. Moreover, they also give more efficiency in terms of system complexity.

We have manufactured large-scaled highly reliable MNOS EEPROMs over the last twenty years. In particular, at the present time, the smart-card microcontroller incorporating an embedded 32-kB MNOS EEPROM is rapidly expanding the markets for mobile applications. It might be said that we have established the conventional MNOS nonvolatile semiconductor memory technology. This paper describes the device design concepts of the MNOS memory, which include the optimization and control of the tunnel oxide film thickness (1.8 nm), and the scaling guideline that considers the charge distribution in the trapping nitride film. We have developed a high-performance MONOS structure and have not found any failure due to the MONOS devices in high-density EEPROM products during 10-year data retention tests after 105 erase/write cycles. The future development of this highly reliable MNOS-type memory will be focussed on the high-density cell structure and high-speed programming method. Recently, some promising ideas for utilizing an MNOS-type memory device, such as 1-Tr/bit cell for byte-erasable full-featured EEPROMs and 2-bit/Tr cell for flash EEPROMs have been proposed. We are convinced that MNOS technology will advance into the area of nonvolatile semiconductor memories because of its high reliability and high yield of products.

A low-voltage operation and highly-reliable nonvoltatile semiconductor memory with a large capacity has been manufactured using 0.8-µm CMOS technology. This 3-volt, 1-Mbit, full-featured MONOS EEPROM has a chip size of 51.3 mm2 and a memory cell size of 23.1µm2. An asymmetric programming voltage method fully exploits the abilities of the MONOS device and provides 10-year data retention after 106 erase/write cycles. Because of its wide-margin circuit design, this EEPROM can also be operated at 5 volts. High-speed read out is provided by using the polycide word line and the differential sense amplifier with a MONOS dummy memory. New functions such as data protection with software and programming-end indication with a toggle bit are added, and chips are TSOP packaged for use in many kinds of portable equipment.