Making information technology (IT) more accessible to elderly users is an important objective, in particular, concerning input devices. In this study, it has been investigated how the aging factor and the letter (character) size of a keyboard affects the efficiency in data entry. In addition, computer experience by the elderly was examined relative to efficiency. The performance measures (entry speed and correctly entered number per min) were twice better in a young group of computer users than in middle-aged and elderly groups. The effect of the size of the keyboard letters on performance was observed for the middle-aged and elderly groups who had no experience using a computer. The young, middle-aged, and elderly groups with computer experience were not affected by the size of the keyboard letters.

In this paper, a novel Wold decomposition algorithm is proposed to address the issue of deterministic component extraction for texture images. This algorithm exploits the wavelet-based singularity detection theory to process both harmonic a nd evanescent features from frequency domain. This exploitation is based on the 2D Lebesgue decomposition theory. When applying multiresolution analysis techniq ue to the power spectrum density (PSD) of a regular homogeneous random field, its indeterministic component will be effectively smoothed, and its deterministic component will remain dominant at coarse scale. By means of propagating these positions to the finest scale, the deterministic component can be properly extracted. From experiment, the proposed algorithm can obtain results that satisfactorily ensure its robustness and efficiency.

This paper presents a technique for improving the SNR and resolution of complex bandpass ΔΣADCs which are used for wireless communication systems such as cellular phone, wireless LAN and Bluetooth. Oversampling and noise-shaping are used to achieve high accuracy of a ΔΣAD modulator. However when a multi-bit internal DAC is used inside a modulator, nonlinearities of the DAC are not noise-shaped and the SNR of the ΔΣADC degrades. For the conversion of complex intermediate frequency (IF) input signals, a complex bandpass ΔΣAD modulator can provide superior performance to a pair of real bandpass ΔΣAD modulators of the same order. This paper proposes a new noise-shaping algorithm--implemented by adding simple digital circuitry--to reduce the effects of nonlinearities in multi-bit DACs of complex bandpass ΔΣAD modulators. We have performed simulation with MATLAB to verify the effectiveness of the algorithm, and the results show that the proposed algorithm can improve the SNR of a complex bandpass ΔΣADC with nonlinear internal multi-bit DACs.

This paper describes the design and implementation of a testbed for predicting master/slave (M/S) programs written using Message Passing Interface (MPI) programs. The testbed, named M/S Emulator (MSE), aims at assisting developers in evaluating the performance of M/S programs and dynamic load-balancing strategies on clusters of PCs. In order to realize this, MSE predicts the communication time by using a realistic parallel computational model, an extension of the LogGPS model. This extended model improves the prediction accuracy on a large number of processors, because it captures the master's bottleneck: the overhead required for retrieving arrival messages from the slaves. Current MSE also employs a best effort emulation method for predicting the calculation time. In our experiments, MSE demonstrated an accurate prediction on clusters, especially on a larger number of nodes. Therefore, we believe that our extended model enables us to analyze the scalability of the M/S program performance.

This paper proposes a new steganographic method utilizing features of JPEG compression. The method embeds secret information using the number of zeroes in a block of quantized DCT coefficients in minimum coding units (MCU) of JPEG images. In the method, we can embed secret information into JPEG images with degradation like that by JPEG compression. Furthermore, the method causes little change of the histogram of quantized DCT coefficients, so it is hard to perceive secret information embedded by the method. The method mainly modifies boundaries between zero and non-zero DCT coefficients, so we can use the low frequency side of DCT coefficients for another steganographic method.

In this paper, we design and implement a fast asynchronous embedded CISC microprocessor, A8051, introducing well-tuned pipeline architecture and enhanced control schemes. This work shows an asynchronous design methodology for a CISC type processor, handling the complicated control structure and various instructions. We tuned the proposed architecture to the 5-stage pipeline, reducing the number of idle stages. For the work, we regrouped the instructions based on the number of the machine cycles identified. A8051 has three enhanced control features to improve the system performance: multi-looping control of the pipeline stage, variable length instruction register to get a multiple word instruction in a time, and branch prediction accelerating. The proposed A8051 was synthesized to a gate level design using a 0.35 µm CMOS standard cell library. Simulation results indicate that A8051 provides about 18 times higher speed than the traditional Intel 8051 and about 5 times higher speed than the previously designed asynchronous 8051. In power consumption, core of A8051 shows 15 times higher MIPS/Watt than the synchronous H8051.

In this paper, we present a novel energy compaction method, called the selective block-wise reordering, which is used with SPIHT (SBR-SPIHT) coding for low rate video coding to enhance the coding efficiency for motion-compensated residuals. In the proposed coding system, the motion estimation and motion compensation schemes of H.263 are used to reduce the temporal redundancy. The residuals are then wavelet transformed. The block-mapping reorganization utilizes the wavelet zerotree relationship that jointly presents the wavelet coefficients from the lowest subband to high frequency subbands at the same spatial location, and allocates each wavelet tree with all descendents to form a wavelet block. The selective multi-layer block-wise reordering technique is then applied to those wavelet blocks that have energy higher than a threshold to enhance the energy compaction by rearranging the significant pixels in a block to the upper left corner based on the magnitude of energy. An improved SPIHT coding is then applied to each wavelet block, either re-ordered or not. The high energy compaction resulting from the block reordering can reduce the number of redundant bits in the sorting pass and improve the quantization efficiency in the refinement pass of SPIHT coding. Simulation results demonstrate that SBR-SPIHT outperforms H.263 by 1.28-0.69 dB on average for various video sequences at very low bit-rates, ranging from 48 to 10 kbps.

A new power-down circuit scheme using data-preserving complementary pass transistor flip-flop circuit for low-power, high-performance Multi-Threshold voltage CMOS (MTCMOS) LSI is presented. The proposed circuit can preserve a stored data during power-down period while maintaining low leakage current without any extra circuit and complex timing design. The flip-flop provides 24% improved delay and 30% less silicon area compared to conventional MTCMOS flip-flop circuit. A 16-bits DSP processor core using the proposed circuit and 0.18 µ m CMOS technology was designed. The DSP chip was successfully operated at 120 MHz, 1.65 V and its total leakage current in power-down mode was four orders smaller than conventional DSP chip.

The classification time required by conventional multi-class SVMs greatly increases as the number of pattern classes increases. This is due to the fact that the needed set of binary class SVMs gets quite large. In this paper, we propose a method to reduce the number of classes by using nearest neighbor rule (NNR) in the principle component analysis and linear discriminant analysis (PCA+LDA) feature subspace. The proposed method reduces the number of face classes by selecting a few classes closest to the test data projected in the PCA+LDA feature subspace. Results of experiment show that our proposed method has a lower error rate than nearest neighbor classification (NNC) method. Though our error rate is comparable to the conventional multi-class SVMs, the classification process of our method is much faster.

The paper presents a novel stroke decomposition approach based on a directional filtering technique for recognizing Chinese characters. The proposed filtering technique uses a set of the second-order Gaussian derivative (SOGD) filters to decompose a character into a number of stroke segments. Moreover, a new Gaussian function is proposed to overcome the general limitation in extracting stroke segments along some fixed and given orientations. The Gaussian function is designed to model the relationship between the orientation and power response of the stroke segment in the filter output. Then, an optimal orientation of the stroke segment can be estimated by finding the maximal power response of the stroke segment. Finally, the effects of decomposition process are analyzed using some simple structural and statistical features extracted from the stroke segments. Experimental results indicate that the proposed SOGD filtering-based approach is very efficient to decompose noisy and degraded character images into a number of stroke segments along an arbitrary orientation. Furthermore, the recognition performance from the application of decomposition process can be improved about 17.31% in test character set.

A new speaker feature extracted from multi-wavelet decomposition for speaker recognition is described. The multi-wavelet decomposition is a multi-scale representation of the covariance matrix. We have combined wavelet transform and the multi-resolution singular value algorithm to decompose eigenvector for speaker feature extraction not at the square matrix. Our results have shown that this multi-wavelet feature introduced better performance than the cepstrum and Δ-cepstrum with respect to the percentages of recognition.

In this paper we propose a new blind adaptive compensator associated with the inverse QRD-RLS (IQRD-RLS) algorithm to adaptively estimate the parameters, related to the effects of gain/phase imbalance and DC offsets occur in the Quadrature demodulator, for compensation. In this new approach the power measurement of the received signal is employed to develop the blind adaptation algorithm for compensator, it does not require any reference signal transmitted from the transmitter and possess the fast convergence rate and better numerical stability. To verify the great improvement, in terms of reducing the effects of the imbalance and offset, over existing techniques computer simulation is carried out for the coherent 16 PSK-communication system. We show that the proposed blind scheme has rapidly convergence rate and the smaller mean square error in steady state.

In the emerging networks, routing may be performed at various levels of the TCP/IP stack, such as datagram, TCP stream or application level, with possibly different message forwarding modes. We formulate an abstract quickest path problem for the transmission of a message of size σ from a source to a destination with the minimum end-to-end delay over a network with bandwidth and delay constraints on the links. We consider six modes for the message forwarding at the nodes reflecting the mechanisms such as circuit switching, store and forward, and their combinations. For each of first five modes, we present O( m2 + mn log n ) time algorithms to compute the quickest path for a given message size σ. For the last mode, the quickest path can be computed in O(m + n log n ) time.

Energy consumption has become one of the most critical constraints in the design of portable multimedia systems. For media applications, address buses between processor and data memory consume a considerable amount of energy due to their large capacitance and frequent accesses. This paper studies impacts of memory data organization on the address bus energy. Our experiments show that the address bus activity is significantly reduced by 50% through exploring memory data organization and encoding address buses.

The alternating variant of the shrinking two-pushdown automaton of Buntrock and Otto (1998) is introduced. It is shown that the class of languages accepted by these automata is contained in the class of deterministic context-sensitive languages, and that it contains a PSPACE-complete language. Hence, the closure of this class of languages under log-space reductions coincides with the complexity class PSPACE.

A VLSI-specific wavelet processing technique has been developed and implemented as a processor in accordance with the JPEG2000 specification. This proposed procedure of discrete wavelet transforms uses an altered calculation equations and makes use of intermediate results through wavelet calculation. The implementation of the proposed procedure is capable of realizing a highly efficient DWT for large size images in spite of using low hardware costs and a small size buffering memory. In order to obtain fast EBCOT processing, three types of parallel processing are introduced in the EBCOT architecture. The processor performs compression of 720480 pixels images with the speed of 30 frames per second (fps) at a required operating frequency as low as 32 MHz or lower. Furthermore, it need not divide an image into tiles so that the problem of deterioration of image quality due to tile division does not occur. A prototype of this processor has been fabricated in a 0.25-µm 5-layer CMOS process. The chip is 10.210.4 mm2 in size and consumes 2.0 W when supplied with 2.5 V and 32 MHz.

This paper presents a new mobility protocol that supports multiple namespaces on IPv6 networks. Our proposed protocol framework allows a mobile node to specify a correspondent node by a name that is defined in any namespace as a node identifier. This technique removes certain restrictions on the space of node identifiers and allows mobile nodes to communicate with each other regardless of their location. Mobile nodes negotiate a pseudo node identifier, which is unique between the two nodes, with a correspondent node that is identified by the name. We make this pseudo node identifier compatible with the IPv6 address format; we can thus use existing IPv6 applications with our proposed mobility framework. This framework is based on Location Independent Network Architecture (LINA), and provides mobility support in a simple fashion and with low protocol overhead. We also demonstrate how to provide anonymity to our mobility protocol by using a dynamic pseudo node identifier. Our prototype implementation shows minimal overhead compared to a conventional IPv6 implementation.

This paper investigates prefix computations on Iterative Arrays (IAs) with sequential input/output mode. We show that, for any language L accepted by a linear-time IA, there is an IA which, given an infinite string a1a2 ai, generates the values of χL(a1),χL(a1a2),,χL(a1a2 ai), at steps 4,16,,4i2,, respectively. Here, χL:Σ*{0,1} is the characteristic function of the language L Σ*, defined as χL(w) = 1 iff w L. We also construct 2i3-time and i4-time prefix algorithms for languages accepted by quadratic-time and cubic-time IAs, respectively.

This paper investigates relationships among deterministic, nondeterministic, and alternating complexity classes defined in the hyperbolic space. We show that (i) every t(n)-time nondeterministic cellular automaton in the hyperbolic space (hyperbolic CA) can be simulated by an O(t4(n))-space deterministic hyperbolic CA, and (ii) every t(n)-space nondeterministic hyperbolic CA can be simulated by an O(t2(n))-time deterministic hyperbolic CA. We also show that nr+-time (non)deterministic hyperbolic CAs are strictly more powerful than nr-time (non)deterministic hyperbolic CAs for any rational constants r 1 and > 0. From the above simulation results and a known separation result, we obtain the following relationships of hyperbolic complexity classes: Ph= NPh = PSPACEh EXPTIMEh= NEXPTIMEh = EXPSPACEh , where Ch is the hyperbolic counterpart of a Euclidean complexity class C. Furthermore, we show that (i) NPh APh unless PSPACE = NEXPTIME, and (ii) APh EXPTIME h.

A new algorithm and architecture to eliminate redundant operations in block-matching (BM) motion estimation is proposed. The key step of this work is to use binary-matching to define image regions with the static background content and then exclude these regions from the actual motion estimation. According to experiments, the approach maintains the highest PSNR, while making as half as less computations in comparison to the adaptive BM or 1/8 of the computations required by the full-search BM. An implementation scheme is outlined.