In this paper, we present a test data compression technique to reduce test data volume for multiscan-based designs. In our method the internal scan chains are divided into equal sized groups and two dictionaries were build to encode either an entire slice or a subset of the slice. Depending on the codeword, the decompressor may load all scan chains or may load only a group of the scan chains, which can enhance the effectiveness of dictionary-based compression. In contrast to previous dictionary coding techniques, even for the CUT with a large number of scan chains, the proposed approach can achieve satisfied reduction in test data volume with a reasonable smaller dictionary. Experimental results showed the proposed test scheme works particularly well for the large ISCAS'89 benchmarks.

This paper presents a VLSI design methodology for the MAC-level DWT/IDWT processor based on a novel limited-resource scheduling algorithm. The r-split Fully-specified Signal Flow Graph (FSFG) of limited-resource FIR filtering has been developed for the scheduling of the MAC-level DWT/IDWT signal processing. Given a set of architecture constraints and DWT parameters, the scheduling algorithm can generate four scheduling matrices that drive the data path to perform the DWT computation. Because the memory for the inter-octave is considered with the register of FIR filter, the memory size is less than the traditional architecture. Besides, based on the limited-resource scheduling algorithm, an automated DWT processor synthesizer has been developed and generates constrained DWT processors in the form of silicon intelligent property (SIP). The DWT SIP can be embedded into a SOC or mapped to program codes for commercial off-the-shelf (COTS) DSP processors with programmable devices. As a result, it has been successfully proven that a variety of DWT SIPs can be efficiently realized by tuning the parameters and applied for signal processing applications.

This paper describes an approach to feature extraction in speech recognition systems using kernel principal component analysis (KPCA). This approach represents speech features as the projection of the mel-cepstral coefficients mapped into a feature space via a non-linear mapping onto the principal components. The non-linear mapping is implicitly performed using the kernel-trick, which is a useful way of not mapping the input space into a feature space explicitly, making this mapping computationally feasible. It is shown that the application of dynamic (Δ) and acceleration (ΔΔ) coefficients, before and/or after the KPCA feature extraction procedure, is essential in order to obtain higher classification performance. Better results were obtained by using this approach when compared to the standard technique.

A new moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each tree and the corresponding links can be determined independently. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute system moments efficiently. Experimental results have demonstrate that the proposed method can indeed obtain accurate moments and is more efficient than the conventional approach.

We propose a practical blind channel identification algorithm based on the principal component analysis. The algorithm estimates (1) the channel order, (2) the noise variance, and then identifies (3) the channel impulse response, from the autocorrelation of the channel output signal without using the eigenvalue and singular-value decomposition. The special features of the proposed algorithm are (1) practical method to find the channel order and (2) reduction of computational complexity. Numerical examples show the effectiveness of the proposed algorithm.

In this paper, we present a new numerical method for the complex approximation of FIR digital filters. Our objective is to design FIR filters with equiripple magnitude and phase errors. The proposed method solves the least squares (LS) problem iteratively. At each iteration, the desired response is updated so as to have an equiripple error. The proposed methods do not require any time-consuming optimization procedure such as the quasi-Newton methods and converge to equiripple solutions quickly. We show some examples to illustrate the advantages of our proposed methods.

In this paper, we propose a formal method for detection of three automation surprises in human-machine interaction; a mode confusion, a refusal state, and a blocking state. The mode confusion arises when a machine is in a different mode from that anticipated by the user, and is the most famous automation surprise. The refusal state is a situation that the machine does not respond to a command the user executes. The blocking state is a situation where an internal event occurs, leading to change of an interface the user does not know. In order to detect these phenomena, we propose a composite model in which a machine and a user model evolve concurrently. We show that the detection of these phenomena in human-machine interaction can be reduced to a reachability problem in the composite model.

Direct digital frequency synthesizers (DDFS) provide fast frequency switching with high spectral purity and are widely used in modern spread spectrum wireless communication systems. ROM-based DDFS uses a ROM lookup table to store the amplitude of a sine wave. A large ROM table is required for high spectral purity. However, a larger ROM uses more area and consumes more power. Several ROM compression methods, including Sunderland technique based on simple trigonometric identities and quantization & error compensation techniques, have been reported. In this paper, we suggest several new techniques to reduce the ROM size. One new technique uses more number of hierarchical levels in ROM structures. Another technique uses simple interpolation techniques combined with hierarchical ROM structures. Experimental results show that the new proposed techniques can reduce the required ROM size up to 24%, when compared to that of a resent approach.

We study analysis of hybrid systems under incomplete knowledge. The class of hybrid systems to be considered is assumed to have the form of a rectangular hybrid automaton such that each constant in invariants and guards is given as a parameter. We develop a method based on symbolic computation that computes an approximation of the discrete behavior of the automaton. We also show an implementation on a constraint logic programming language.

An experimental model of a redox microarray, which provides a foundation for constructing future massively parallel molecular computers, is proposed. The operation of a redox microarray is confirmed, using an experimental setup based on an array of microelectrodes with analog integrated circuits.

For large circuits, vector compaction techniques could provide a faster solution for power estimation with reasonable accuracy. Because traditional sampling approach will incur useless transitions between every sampled pattern pairs after they are concatenated into a single sequence for simulation, we proposed a vector compaction method with grouping and single-sequence consecutive sampling technique to solve this problem. However, it is very possible that we cannot find a perfect consecutive sequence without any undesired transitions. In such cases, the compaction ratio of the sequence length may not be improved too much. In this paper, we propose an efficient approach to relax the limitation a little bit such that multiple consecutive sequences are allowed. We also propose an algorithm to reduce the number of sequences instead of setting the number as one to find better solutions for vector compaction problem. As demonstrated in the experimental results, the average compaction ratio and speedup can be significantly improved by using this new approach.

Quantum dots are one of the possible building blocks for the quantum computing device. We discuss on use of carbon nanotubes for fabrication of the quantum dot, in terms of their unique physical properties and energy scales which might be advantageous for functionalities of the quantum computing device. Simple schemes of a charge qubit and a spin qubit are described, followed by the current status of the fabrication and transport measurements of the nanotube quantum dot. Based on the basic properties and the estimated energy scales of the dot, we discuss advantages and problems of the carbon nanotube for the quantum computing device. The nanotube quantum dot may have a great advantage for the spin qubit.

Imaging techniques for robots are important and meaningful in the near future. Pulse radar systems have a great potential for shape estimation and locationing of targets. They have an advantage that they can be used even in critical situations where optical techniques cannot be used. It is thus required to develop high-resolution imaging algorithms for pulse radar systems. High-resolution imaging algorithms utilize the carrier phase of received signals. However, their estimation accuracy suffers degradation due to phase rotation of the received signal because the phase depends on the shape of the target. In this paper, we propose a phase compensation algorithm for high-resolution pulse radar systems. The proposed algorithm works well with SEABED algorithm, which is a non-parametric algorithm of estimating target shapes based on a reversible transform. The theory is presented first and numerical simulation results follow. We show the estimation accuracy is remarkably improved without sacrificing the resolution using the proposed algorithm.

This paper describes a new fast learning algorithm for Self-Organizing Map employing a "rough comparison winner-take-all" and its digital hardware architecture. In rough comparison winner-take-all algorithm, the winner unit is roughly and strictly assigned in early and later learning stage, respectively. It realizes both of high accuracy and fast learning. The digital hardware of the self-organizing map with proposed WTA algorithm is implemented using FPGA. Experimental results show that the designed hardware is superior to other hardware with respect to calculation speed.

A reaction-diffusion computer is a large-scale array of elementary processors, micro-volumes of chemical medium, which act, change their states determined by chemical reactions, concurrently and interact locally, via local diffusion of chemical species; it transforms data to results, both represented by concentration profiles of chemical species, by traveling and colliding waves in spatially extended chemical media. We show that reaction-diffusion processors, simulated or experimental, can solve a variety of tasks, including computational geometry, robot navigation, logics and arithmetics.

In this paper, introducing a stochastic hill-climbing dynamics into an optimal competitive Hopfield network model (OCHOM), we propose a new algorithm that permits temporary energy increases, which helps the OCHOM escape from local minima. In graph theory, a clique is a completely connected subgraph and the maximum clique problem (MCP) is to find a clique of maximum size of a graph. The MCP is a classic optimization problem in computer science and in graph theory with many real-world applications, and is also known to be NP-complete. Recently, Galan-Marin et al. proposed the OCHOM for the MCP. It can guarantee convergence to a global/local minimum of energy function, and performs better than other competitive neural approaches. However, the OCHOM has no mechanism to escape from local minima. The proposed algorithm introduces stochastic hill-climbing dynamics which helps the OCHOM escape from local minima, and it is applied to the MCP. A number of instances have been simulated to verify the proposed algorithm.

This paper describes a 0.13 µm CMOS Logic process compatible single poly gate type non-volatile (NV) memory with a differential cell architecture, which is tailored for a rewritable FUSE (CMOS-FUSE) for System-on-a Chip (SoC). This paper features the following points; 1) firstly quantified how much important is avoiding any additional process cost and area penalty rather than reducing the area of memory cell itself from the chip cost point of view for the new SoC applications. CMOS FUSE can provide cost-competitive than the high-density NV memories (50-fold higher density with 20% additional cost relative to CMOS FUSE) in the capacity range of 200 kbit for the SoC occupied the logic area of 40 mm2. 2) firstly discussed in detail how much the differential cell architecture can change a data retention characteristics including an activation energy (Ea), failure-rate, and tail-bits issues relative to the conventional one based on the measured data of 0.13 µm devices. Based on the measured data retention characteristics at 300, 250, and 200, it is found that the proposed differential approach makes it possible to increase Ea by 1.5 times (from 1.52 eV to 2.23 eV), which means it can be expected to realize a 20000-fold longer data retention characteristics at 105. Even if considering the tail-bit issues for mass-production, an over 700-fold longer data retention characteristics at 105 can be expected while keeping the same failure rate (0.01 ppm) relative to the conventional OR-logical architecture. No significant Vt shifts ( 140 mV and 200 mV) were observed even after applying surge stress of +2200 V from I/O pad and 1000-times cycling of write and erase operations, respectively. In addition, 1024-bit CMOS-FUSE module has been embedded in the SoC without any additional area penalty by being laid out just beneath the power ring for SRAM macro and the stable memory read operation was verified at VDD=1.0 V under a severe I/O switching noise and an unstable VDD/GND condition in the power up sequence.

Energy consumption is one of the most critical constraints in the design of portable embedded systems. This paper describes an empirical study about the impacts of compiler optimizations on the energy consumption of the address bus between processor and instruction memory. Experiments using a number of real-world applications are presented, and the results show that transitions on the instruction address bus can be significantly reduced (by 85% on the average) by the compiler optimizations together with bus encoding.

We show that the necessary and sufficient condition for the existence of a balanced bowtie decomposition of the symmetric complete multi-digraph is n 5 and λ(n-1) 0 (mod 6). Decomposition algorithms are also given.

The operation of a polarization mode dispersion (PMD) compensator using a polarizer and a Faraday rotator-based polarization controller (FRPC) is analyzed in detail, and the compensation performance is experimentally evaluated in 40 Gbit/s operation. The evaluation results show that a wide range of differential group delay over a bit period can almost be completely compensated using the PMD compensator. The characteristics of electrical spectrum-based signal monitoring methods are investigated in detail, and the results shows advantages of a low frequency band monitoring method that produces about double the wider dynamic range than a fundamental repetition frequency monitoring method. The automated PMD compensator using a polarizer and a FRPC driven by the low frequency band monitoring method is experimentally investigated using a terrestrial 40 Gbit/s wavelength division multiplexing system involving 350-km installed single-mode fibers. The PMD compensator produces highly stable signal performance in the field environment for a long term and reduces the standard deviation of the Q-factor distribution.