A mobile hotspot is a moving vehicle that hosts an Access Point (AP) such as train, bus and subway where users in these vehicles connect to external cellular network through AP to access their internet services. To meet Quality of Service (QoS) requirements, typically throughput and/or delay, a Call Admission Control (CAC) is needed to restrict the number of users accepted by the AP. In this paper, we analyze a modified guard channel scheme as CAC for mobile hotspot as follows: During a mobile hotspot is in the stop-state, we adopt a guard channel scheme where the optimal number of resource units is reserved for vertical handoff users from cellular network to WLAN. During a mobile hotspot is in the move-state, there are no handoff calls and so no resources for handoff calls are reserved in order to maximize the utility of the WLAN capacity. We model call's arrival and departure processes by Markov Modulated Poisson Process (MMPP) and then we model our CAC by 2-dimensional continuous time Markov chain (CTMC) for single traffic and 3-dimensional CTMC for two types of traffic. We solve steady-state probabilities by the Quasi-Birth and Death (QBD) method and we get various performance measures such as the new call blocking probabilities, the handoff call dropping probabilities and the channel utilizations. We compare our CAC with the conventional guard channel scheme which the number of guard resources is fixed all the time regardless of states of the mobile hotspot. Finally, we find the optimal threshold value on the amount of resources to be reserved for the handoff call subject to a strict constraint on the handoff call dropping probability.

The gathering problem of anonymous and oblivious mobile robots is one of the fundamental problems in the theoretical mobile robotics. We consider the gathering problem in unoriented and anonymous rings, which requires that all robots eventually keep their positions at a common non-predefined node. Since the gathering problem cannot be solved without any additional capability to robots, all the previous results assume some capability of robots, such as the agreement of local view. In this paper, we focus on the multiplicity detection capability. This paper presents a deterministic gathering algorithm with local-weak multiplicity detection, which provides a robot with information about whether its current node has more than one robot or not. This assumption is strictly weaker than that in previous works. Our algorithm achieves the gathering from an aperiodic and asymmetric configuration with 2 < k < n/2 robots, where n is the number of nodes. We also show that our algorithm is asymptotically time-optimal one, i.e., the time complexity of our algorithm is O(n). Interestingly, despite the weaker assumption, it achieves significant improvement compared to the previous algorithm, which takes O(kn) time for k robots.

The voltage biased SQUID Bootstrap Circuit (SBC) was recently demonstrated for direct readout of SQUID signals. The SBC combines current- and voltage-feedbacks in one circuit to suppress the preamplifier noise. It offers not only a good noise performance, but also wide tolerance of SQUID parameters. Using SBC gradiometer, the bio-magnetic signals were successfully measured. In this paper, we overview the concept of SBC and its applications.

In this paper, we consider a problem of simultaneously optimizing a sequence of graphs and a route which exhaustively visits the vertices from each pair of successive graphs in the sequence. This type of problem arises from repetitive routing of grasp-and-delivery robots used in the production of printed circuit boards. The problem is formulated as follows. We are given a metric graph G*=(V*,E*), a set of m+1 disjoint subsets Ci ⊆ V* of vertices with |Ci|=n, i=0,1,...,m, and a starting vertex s ∈ C0. We seek to find a sequence π=(Ci1, Ci2, ..., Cim) of the subsets of vertices and a shortest walk P which visits all (m+1)n vertices in G* in such a way that after starting from s, the walk alternately visits the vertices in Cik-1 and Cik, for k=1,2,...,m (i0=0). Thus, P is a walk with m(2n-1) edges obtained by concatenating m alternating Hamiltonian paths between Cik-1 and Cik, k=1,2,...,m. In this paper, we show that an approximate sequence of subsets of vertices and an approximate walk with at most three times the optimal route length can be found in polynomial time.

This paper proposes an enhanced feature detection method for the OFDM signals of digital TV (DTV) standards, namely Digital Video Broadcasting-Terrestrial (DVB-T) and Integrated Services Digital Broadcasting-Terrestrial (ISDB-T). The proposed method exploits property of time-domain sliding correlation results of DTV signals with the pilots that are inserted into OFDM symbols. Some correlation outputs are much larger than the remaining outputs and are called correlation peaks here, and, the distance between their positions in the correlation output sequence keep constant regardless of the received DTV timings. The proposed method then derives sensing test statistic with improved SNR by aggregating the correlation peaks based on their positions. Performance of the proposed method is evaluated by both computer simulation and hardware implementation. Simulation results for DVB-T detection verify that compared to the optimal conventional sensing method, the proposed method achieves superior sensing performance. It reduces sampling time by about 25% for the same sensing performance while increasing computational complexity by around 0.0001%. Hardware performance further verifies that the proposed method is able to accurately detect ISDB-T at the low SNR of -14.5 dB by employing 8 OFDM symbol durations of samples.

With process technology scaling, a heat problem in ICs is becoming a serious issue. Since high temperature adversely impacts on reliability, design costs, and leakage power, it is necessary to incorporate thermal-aware synthesis into IC design flows. In particular, hot spots are serious concerns where a chip is locally too much heated and reducing the peak temperature inside a chip is very important. On the other hand, increasing the average interconnect delays is also becoming a serious issue. By using RDR architectures (Regular-Distributed-Register architectures), the interconnect delays can be easily estimated and their influence can be much reduced even in high-level synthesis. In this paper, we propose a thermal-aware high-level synthesis algorithm for RDR architectures. The RDR architecture divides the entire chip into islands and each island has uniform area. Our algorithm balances the energy consumption among islands through re-binding to functional units. By allocating some new additional functional units to vacant areas on islands, our algorithm further balances the energy consumption among islands and thus reduces the peak temperature. Experimental results demonstrate that our algorithm reduces the peak temperature by up to 9.1% compared with the conventional approach.

This paper introduces novel high-speed and low-power boosted level converters for use in dual-supply systems. The proposed level converters adopt a voltage boosting at the gate of pull-down transistors to improve driving speed and reduce contention problem. Comparison results in a 0.13-µm CMOS process indicated that the proposed level converters provided up to 70% delay reduction with up to 57% power-delay product (PDP) reduction as compared to conventional level converters.

This paper focuses on the latest research of switching arc both in vacuum and SF6 substitutes in our group. The crucial characteristics of vacuum arc are illustrated, including the motion and distribution of single cathode spot and multiple cathode spots, the influence of axial magnetic field on arc plasma characteristics, the influence of composite magnetic field on cathode jets, and the study of anode activities. Meanwhile, the arc characteristics in SF6 and its substitutes (Ar, CO2 and N2) at different pressures and gap distances are investigated by experiments and simulation.

A low-power switching method using a bootstrapping circuit is proposed for a high-speed output driver of transmitter. Compared with a conventional output driver, the proposed scheme employs only nMOSFETs to transmit data. The bootstrapping circuit ensures the proper switching of nMOSFET. The proposed scheme is simulated and fabricated using a 0.18 µm CMOS technology, showing 10.2% lower power consumption than a conventional switching driver at 2.5 Gb/s data rate.

This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18 µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6 V. The designed IA achieves 30 dB of closed-loop gain, 101 dB of common-mode rejection ratio (CMRR) at 50 Hz, 80 dB of power-supply rejection ratio (PSRR) at 50 Hz, thermal noise floor of 53.4 nV/, current consumption of 14 µA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6 V supply from a 0.8–1.0 V energy harvesting power source. It achieves power supply rejection (PSR) of 42 dB at frequency of 1 MHz. A cascode compensated pseudo differential amplifier is used as the filter's building block for low power design. The filter's single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6 dB of signal-to-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100 Hz sinusoidal maximum input signal, bandwidth of 2 kHz, and power consumption of 51.2 µW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18 µm CMOS process.

With the proliferation of IEEE 802.11 wireless local area networks, large numbers of wireless access points have been deployed, and it is often the case that a user can detect several access points simultaneously in dense metropolitan areas. Most owners, however, encrypt their networks to prevent the public from accessing them due to the increased traffic and security risk. In this work, we use pricing as an incentive mechanism to motivate the owners to share their networks with the public, while at the same time satisfying users' service demand. Specifically, we propose a “federated network” concept, in which radio resources of various wireless local area networks are managed together. Our algorithm identifies two candidate access points with the lowest price being offered (if available) to each user. We then model the price announcements of access points as a game, and characterize the Nash Equilibrium of the system. The efficiency of the Nash Equilibrium solution is evaluated via simulation studies as well.

Obtaining a compact representation of a large-size feature map built by mapper robots is a critical issue in recent mobile robotics. This “map compression” problem is explored from a novel perspective of dictionary-based data compression techniques in the paper. The primary contribution of the paper is the proposal of the dictionary-based map compression approach. A map compression system is presented by employing RANSAC map matching and sparse coding as building blocks. The effectiveness levels of the proposed techniques is investigated in terms of map compression ratio, compression speed, the retrieval performance of compressed/decompressed maps, as well as applications to the Kolmogorov complexity.

A bootstrapped analog switch with constant on-resistance is proposed for the successive approximation (SA) analog-to-digital converters (ADCs) that have many input-sampling switches. The initialization circuit, which is composed of a short pulse generator and a transmission gate, improves the linearity of the proposed bootstrapped analog switch by reducing the effect of the capacitive load. To evaluate the proposed bootstrapped analog switch, the 10-bit 1 MS/s CMOS SA ADC with a rail-to-rail differential input signal was designed by using a 0.18 µm CMOS process with 1.0 V supply voltage. The proposed bootstrapped analog switch reduced the maximum VGS variation of the conventional bootstrapped analog switch by 67%. It also enhanced the signal to noise-distortion ratio of the SA ADC by 4.8 dB when the capacitance of its gate node is 100 fF, and this improvement was maximized when the capacitance of its gate node increases.

In this paper, we study the decentralized coverage control problem for an environment using a group of autonomous mobile robots with nonholonomic kinematic and dynamic constraints. In comparison with standard coverage control procedures, we develop a combined controller for Voronoi-based coverage approach in which kinematic and dynamic constraints of the actual mobile sensing robots are incorporated into the controller design. Furthermore, a collision avoidance component is added in the kinematic controller in order to guarantee a collision free coverage of the area. The convergence of the network to the optimal sensing configuration is proven with a Lyapunov-type analysis. Numerical simulations are provided approving the effectiveness of the proposed method through several experimental scenarios.

Robotic systems operating in the real-world have to cope with unforeseen events by determining appropriate decisions based on noisy or partial knowledge. In this respect high functional robots are equipped with many sensors and actuators and run multiple processing modules in parallel. The resulting complexity is even further increased in case of cooperative multi-robot systems, since mechanisms for joint operation are needed. In this paper a complete and modular framework that handles this complexity in multi-robot systems is presented. It provides efficient exchange of generated data as well as a generic scheme for task execution and robot coordination.

Silicon-quantum-dots (Si-QDs) with an areal density as high as 1012 cm - 2 were self-assembled on thermally-grown SiO2 by low pressure CVD using Si2H6, in which OH-terminated SiO2 surface prior to the Si CVD was exposed to GeH4 to create nucleation sites uniformly. After thermal oxidation of Si-QDs surface, two-dimensional electronic transport through the Si-QDs array was measured with co-planar Al electrodes evaporated on the array surface. Random telegraph signals were clearly observed at constant applied bias conditions in dark condition and under light irradiation at room temperature. The result indicates the charging and discharging of a dot adjacent to the percolation current path in the dots array.

We propose a character size optimization technique to reduce the number of EB shots of multi-column-cell (MCC) lithographic systems in which transistor patterns are projected with multiple column cells in parallel. Each and every column cell is capable of projecting patterns with character projection (CP) and variable shaped beam (VSB) methods. Seeking the optimal character size of characters contributes to minimizing the number of EB shots and reducing the fabrication cost for ICs. Experimental results show that the character size optimization achieved 70.6% less EB shots in the best case with an available electron beam (EB) size. Our technique also achieved 40.6% less EB shots in the best case than a conventional character sizing technique.

System implementation for e-Government initiatives should be reliable. Unreliable system implementation could, on the one hand, be insufficient to fulfill basic system requirements, and more seriously on the other hand, break the trust of citizens on governments. The objective of this paper is to advocate the use of formal methods in general, the OTS/CafeOBJ method in particular in this paper, to help develop reliable system implementation for e-Government initiatives. An experiment with the OTS/CafeOBJ method on an e-Government messaging framework proposed for providing citizens with seamless public services is described to back up our advocation. Two previously not well-clarified problems of the framework and their potential harm realized in this experiment are reported, and possible ways of revisions to the framework are suggested as well. The revisions are proved to be sufficient for making the framework satisfy certain desired properties.

We first consider a variant of the Schmidt-Samoa-Takagi encryption scheme without losing additively homomorphic properties. We show that this variant is secure in the sense of IND-CPA under the decisional composite residuosity assumption, and of OW-CPA under the assumption on the hardness of factoring n=p2q. Second, we introduce new algebraic properties "affine" and "pre-image restriction," which are closely related to homomorphicity. Intuitively, "affine" is a tuple of functions which have a special homomorphic property, and "pre-image restriction" is a function which can restrict the receiver to having information on the encrypted message. Then, we propose an encryption scheme with primitive power roots of unity in (Z/ns+1). We show that our scheme has, in addition to the additively homomorphic property, the above algebraic properties. In addition to the properties, we also show that the encryption scheme is secure in the sense of OW-CPA and IND-CPA under new number theoretic assumptions.

In the OTS/CafeOBJ method, software specifications are described in CafeOBJ executable formal specification language, and verification is done by giving scripts to the CafeOBJ system. The script is called a proof score. In this study, we propose a test case generator from an OTS/CafeOBJ specification together with a proof score. Our test case generator gives test cases by analyzing the proof score. The test cases are used to test whether an implementation satisfies the specification and the property verified by the proof score. Since a proof score involves important information for verifying a property, the generated test cases are also expected to be suitable to test the property.