It is known that the original Grover Search (GS) can be modified to use a general value for the phase θ of the diffusion transform. Then, if the number of answers is relatively large, this modified GS can find one of the answers with probability one in a single iteration. However, such a quick and error-free GS can only be possible if we can initially adjust the value of θ correctly against the number of answers, and this seems very hard in usual occasions. A natural question now arises: Can we enjoy a merit even if GS is used without such an adjustment? In this paper, we give a positive answer using the balls-and-bins game in which the random sampling of bins is replaced by the quantum sampling, i.e., a single round of modified GS. It is shown that by using the quantum sampling: (i) The maximum load can be improved quadratically for the static model of the game and this improvement is optimal. (ii) That is also improved to O(1) for the continuous model if we have a certain knowledge about the total number of balls in the bins after the system becomes stable.

In orthogonal frequency division multiplexing (OFDM) systems with differential phase shift keying (DPSK), it is possible to apply differential modulation either in the time or frequency domain depending on the condition of fading channels, such as the Doppler frequency shift and the delay spread. This paper proposes a simple calculation method, that is, an approximate closed-form equation of the bit error rate (BER) in DPSK/OFDM systems mentioned above over both time and frequency selective Rician fading channels. The validity of the proposed method is demonstrated by the fact that the BER performances given by the derived equation coincide with those by Monte Carlo simulation.

We discuss a typical profile of the k-error linear complexity for balanced binary exponent periodic sequences and the number of periodic distinct sequences by their profiles. A numerical example with period 16 is also shown.

In this paper, we present a noble pattern synthesis method of linear and planar array antennas, with non-uniform spacing, for simultaneous reduction of their side-lobe level and pattern distortion during beam steering. In the case of linear array, the Gauss-Newton method is applied to adjust the positions of elements, providing an optimal linear array in the sense of side-lobe level and pattern distortion. In the case of planar array, the concept of thinned array combined with non-uniformly spaced array is applied to obtain an optimal two dimensional (2-D) planar array structure under some constraints. The optimized non-uniformly spaced linear array is extended to the 2-D planar array structure, and it is used as an initial planar array geometry. Next, we further modify the initial 2-D planar array geometry with the aid of thinned array theory in order to reduce the maximum side-lobe level. This is implemented by a genetic algorithm under some constraints, minimizing the maximum side-lobe level of the 2-D planar array. It is shown that the proposed method can significantly reduce the pattern distortion as well as the side-lobe level, although the beam direction is scanned.

This work describes a 2.4 GHz frequency synthesizer based on a delay-locked loop (DLL). Because the proposed frequency synthesizer is basically developed from a DLL, it has no jitter accumulation thereby resulting in a low close-in phase noise of -105 dBc/Hz. Although only 9 delay cells are used, the proposed delay cell reusing scheme realizes frequency multiplication factors greater than 240 and provides multiple frequency output with the resolution of phase detector (PD) comparison frequency. This architecture has been verified by implementing the synthesizer in a 0.18 µm CMOS technology.

In multicarrier code division multiple access (MC-CDMA) systems, the orthogonality among the spreading codes is destroyed because the channels exhibit frequency-selective fading and the despreading stage performs gain control; that is, inter-code interference (ICI) can significantly degrade system performance. This paper proposes an optimum spreading code assignment method that reflects our analysis of ICI for up and downlink MC-CDMA cellular systems over correlated frequency-selective Rayleigh fading channels. At first, we derive theoretical expressions for the desired-to-undesired signal power ratio (DUR) as a quantitative representation of ICI; computer simulation results demonstrate the validity of the analytical results. Next, based on the ICI imbalance among code pairs, we assign specific spreading codes to users to minimize ICI (in short, to maximize the multiplexing performance); our proposed method considers the quality of service (QoS) policy of users or operators. We show that the proposed method yields better performance, in terms of DUR, than the conventional methods. The proposed method can maximize the multiplexing performance of a MC-CDMA cellular system once the channel model, spreading sequence, and combining strategy have been set. Three combining strategies are examined at the despreading stage for the uplink, equal gain combining (EGC), orthogonality restoring combining (ORC), and maximum ratio combining (MRC), while two are considered for the downlink, EGC and MRC.

A challenge to an automated layout of analog ICs starts with the insight into high quality placements crafted by experts. We observe first that matched devices or elemental functions such as input, output, amplifiers, etc are clustered. Second, devices in the same cluster are located faithfully to the drawn schema. Third, these two features are simultaneously fulfilled in a well-compacted placement. This paper proposes a novel device-level placement that simulates the above features based on Sequence-Pair. A slight modification of the meaning, say, of relation "A is left-of B" to relation "A is not right-of B" enlarges the freedom and allows a neater compaction of clusters allowing zigzag border curves. As the consequence, clusters are placed faithfully to relative position in the schema. We tested our algorithm for industrial instances and compared results with those by manual design. The results showed better features in performance figures than the those of manual designs by, on average, 13.5% and 21.2% with respect to the area and total net-length.

This paper presents a fuzzy model-based approach for synchronization of time-delay chaotic system with input saturation. Time-delay chaotic drive and response system is respectively represented by Takagi-Sugeno (T-S) fuzzy model. Specially, the response system contains input saturation. Using the unidirectional linear error feedback and the parallel distributed compensation (PDC) scheme, we design fuzzy chaotic synchronization system and analyze local stability for synchronization error dynamics. Since time-delay in the transmission channel always exists, we also take it into consideration. The sufficient condition for the local stability of the fuzzy synchronization system with input saturation and channel time-delay is derived by applying Lyapunov-Krasovskii theory and solving linear matrix inequalities (LMI's) problem. Numerical examples are given to demonstrate the validity of the proposed approach.

Discrete Wavelet Multi-carrier Transceiver (DWMT) system, which can be viewed as a kind of OFDM, has many advantages because it uses wavelets as its base functions. In this paper we present a new sub-carrier frequency offset correction method for DWMT systems with little assistant information. The essential ideal of this algorithm is: when an orthogonal multi-carrier system is of perfect frequency synchronize, the demodulated signals of different sub-carriers are independent of each other. Whereas when frequency offset exists, intercarrier interference will distort the demodulated signal, i.e. every demodulated signal is the sum of several modulated signals' projects on the demodulating frequency. So the adjacent demodulated signals consist of the element of the same modulated signal, and these demodulated signals are correlated with each other. The degree that they correlated with each other depends on sub-carrier relative frequency offset. Since that little assistant information is used in this algorithm the spectrum efficiency can be largely increased. Simulation results shown that if the number of the sub-carrier of the DWMT system is bigger than 1000, the relative frequency offset can be limited in 2%.

A floorplan specifies the layout of modules in very large scale integration (VLSI) design, and a new code, called the EQ-sequence, for representing a floorplan is presented in this paper. The EQ-sequence is based on a Q-sequence. The EQ-sequence can preserve the adjacent relationships of rooms on a floorplan, but the Q-sequence cannot. The algorithms for encoding, moving and decoding of an EQ-sequence are introduced. With the EQ-sequence, we can check whether two modules abut each other on a floorplan. It has been proved that any floorplan of n rooms is uniquely encoded by an EQ-sequence and any EQ-sequence is uniquely decoded to a floorplan, both in O(n) time.

Digital cinema will continue, for some time, to use image signals converted from the density values of film stock through some form of digitization. This paper investigates the required numbers of quantization bits for both intensity and density. Equations for the color differences created by quantization distortion are derived on the premise that the uniform color space L* a* b* can be used to evaluate color differences in digitized pictorial color images. The location of the quantized sample that yields the maximum color difference in the color gamut is theoretically analyzed with the proviso that the color difference must be below the perceivable limit of human visual systems. The result shows that the maximum color difference is located on a ridge line or a surface of the color gamut. This can reduce the computational burden for determining the required precision for color quantization. Design examples of quantization resolution are also shown by applying the proposed evaluation method to three actual color spaces: NTSC, HDTV, and ROMM.

This paper proposes a simple control method to improve the ignition behavior of cold cathode fluorescent lamp (CCFL) in digital-dimming control. Due to restriking manipulation in digital-dimming mode, the lamp life of CCFL is reduced substantially. To extend the lamp life, we realize a digital-dimming controller with soft-starting technique (DDC-SST) to reduce the high ignition voltage and to eliminate the ignition current spike. The half-bridge resonant inverter is employed in the presented backlight system. Complete analysis and design considerations are discussed in detail in this paper. Simulation and experimental results are close to the theoretical prediction. The overall efficiency of the system achieved at the rated power is over 91%. The ignition voltage is reduced about 30% without any lamp current spike occurred under digital-dimming operation.

In this paper a new method for the determination of the double layer capacitance and the internal inductance of a cell or battery is described. The resonance frequency of the double layer capacity with the internal inductance is determined by means of a phase measurement. The method can be used during operation of the battery. During a constant current discharge it is possible to predict the available discharge time from the resonance frequency at the start of the discharge and the actual resonance frequency. The method is tested with success on lead-acid batteries (VRLA, Plante) and nickel-cadmium batteries and it shows that the active surface is proportional to the state-of-charge (SOC). For primary zinc-MnO2 cells the measured electrical capacitance is not simply related to SOC.

New Recommendation and Future Standards highlight the Power Factor Correction (PFC) converter as a basic requirement for switching power supplies. Most high-frequency power factor correctors use resistor emulation to achieve a near-unity power factor and a small line current distortion. This technique requires forcing the input current with an average-current-mode control to follow the input voltage. Stability of this system was discussed previously by using some linear models. However, in this paper, two nonlinear phenomena have been encountered in the PFC circuit, period doubling bifurcation and chaos. Detection of these new instability phenomena in the stable regions predicted by the prior linear PFC models makes us more susceptible towards them, and reveals the need to consider a nonlinear models. A nonlinear model performing the practical operation of a boost PFC converter has been developed. Then, a simplified and accurate nonlinear model has been proposed and verified experimentally. As a result from this model, instability maps have been introduced to determine the boundary between stable and unstable operating ranges. Then, the period doubling bifurcation has been studied through a new proposed technique based on the capacitor storage energy. It is cleared that, As the load lessens, a required extra storage power is needed to achieve the significant increase in the output voltage. Then, if the PFC system can provide this extra energy, the operation can reach stability with new zero-storage energy else the system will have double-line zero energy that is period doubling bifurcation.

Discrete-time queueing models have been studied for many years because of their direct applicability in the performance evaluation of digital communication system and networks, where buffers are used to temporarily store information packets which cannot be transmitted instantaneously. In this paper, we investigate the behavior of a discrete-time multiserver buffer system with infinite buffer size. Packets arrive in the system according to a two-state correlated arrival process. The service times of the packets are assumed to be independent and identically distributed according to a geometric distribution. We present an analytical technique, based on the use of generating functions, for the analysis of the system. Explicit expressions are obtained for the mean values, the variances and the tail distributions of the system contents and the packet delay. The influence of the various model parameters on the behavior of the system is shown by means of some numerical examples.

The notion of effective bandwidth provides an elegant and powerful mathematical basis for the provision of QoS-assured services over IP networks. In this paper, we propose a semi-parametric estimator of effective bandwidth, called Gaussian estimator using buffer masurement, for superposition of sources in IP networks. In contrast to most existing proposals concerning the effective bandwidth estimator, our proposal works based on a small set of measurements of the workload in the buffer of a router. We analytically show the property of the proposed estimator with respect to the dependence on the service rate. We provide numerical results to show that our proposed estimator is more accurate than estimators that rely only on the amount of traffic from sources.

This paper introduces an efficient affine projection algorithm (APA) using iterative hyperplane projection. The inherent effectiveness against the rank deficient problem has led APA to be the preferred algorithm to be employed for various applications over other variety of fast converging adaptation algorithms. However, the amount of complexity of the conventional APA could not be negligible because of the accomplishment of sample matrix inversion (SMI). Another issue is that the "shifting invariance property," which is typically exploited for single channel case, does not hold ground for space-time decision-directed equalizer (STDE) application deployed in single-input-multi-output (SIMO) systems. Therefore, fast adaptation schemes, such as fast traversal filter based APA (FTF-APA), becomes impossible to utilize. The motivation of this paper deliberates on finding an effective algorithm on the basis of APA, which yields low complexity while sustaining fast convergence as well as excellent tracking ability. The performance of the proposed method is evaluated under wireless SIMO channel in respect to bit error rate (BER) behavior and computational complexity, and upon completion, the validity is confirmed. The performance of the proposed method is evaluated under wireless SIMO channel in respect to bit error rate (BER) behavior and computational complexity, and upon completion, the validity is confirmed.

This paper presents a dual-frequency microstrip antenna for both 2 GHz and 5 GHz for a dual-band receiver. For a simple structure and low cost design, the microstrip feed circuit is designed on the same substrate as the antenna elements. Each antenna element is directly fed by the microstrip line, and the open stubs are loaded on the feed line of 2 GHz to suppress the higher order mode resonances between 2 GHz and 5 GHz. The feed line length of each antenna is adjusted so as to change it to the open condition at the other element frequency at the feed point. In addition, we propose the antenna structure in which two antenna elements for 2 GHz are split and placed at either sides of the 5 GHz antenna to coincide with the center positions of each antenna element. We investigate the proposed antenna by calculations and measurements to show the combiner free design for the dual band antenna.

In this paper, we propose an autonomously distributed QoS control method for MPEG video streaming in a wide area network. The capacity of the links and the characteristics of video streams change dynamically. However, managing the condition of all the links and streams in the network is difficult. In the proposed method, the routers in the network monitor the conditions of the links and streams locally and control the transmission rate of the stream server. Picture-quality oriented fairness is achieved by reducing the transmission rate of the streams with the higher PSNR in the bottleneck link. The computer simulation results show that the proposed method can be applied to a wide area network.

Latch-based circuits have advantages for timing and are widely used for high-speed custom circuits. ASIC design flows, however, are based on circuits with flip-flops. This paper describes a new timing optimization algorithm by replacing the flip-flops in high-end ASICs by latches without changing the functionality of the circuits. Timing is optimized by using a fixed-phase retiming minimizing the impact of clock skew and jitter. A formal equivalence verification method that assures the logical correctness of the latch-replaced circuits is also proposed. Experimental results show that the optimization algorithm decreases the delay of benchmark circuits by as much as 17%.