This paper describes the circuit design procedure of the zero-current soft switching (ZCS) high frequency inverter for induction heating uses. Its output power can be regulated from its maximum to minimum by the instantaneous current vector control scheme using phase shift control between switching units at a fixed frequency. In addition, it can be safely operated since no extraordinarily high voltage or current results even at a short-circuit period at the load. Also, its overall efficiency reaches 90%. The detailed load and frequency characteristics of the inverter are elucidated by the computer-aided simulation. Then, the circuit design procedure is presented, and practical numerical examples are obtained according to this procedure which reveal that the inverter is highly practical and the design procedure is effective. The trial inverters yielding 2 kW or 4 kW were actually prepared. The observed values of the voltages and currents of the inverters were found to be in good agreement with the calculated ones. These facts certificate the validity of the proposed design procedure.

We fabricated ramp-edge junctions with barriers by modifying surface and integrating ground-planes. The fabricated junctions had current-voltage characteristics consistent with the resistive shunted-junction model. We also obtained a 1-sigma spread in the critical current of 7.9% for 100 junctions at 4.2 K. The ground-plane reduced the sheet inductance of a stripline by a factor of 3. The quality of the ground-plane was improved by using an anneal in oxygen atmosphere after fabrication. The sheet inductance of a counter-electrode with a ground-plane was 1.0 pH per square at 4.2 K.

A new class of least-squares algorithms is presented for adaptive filtering. The idea is to use a fixed set of directions and perform line search with one direction at a time in a cyclic fashion. These algorithms are called Euclidean Direction Search (EDS) algorithms. The fast version of this class is called the Fast-EDS or FEDS algorithm. It is shown to have O(N) computational complexity and a convergence rate comparable to that of the RLS algorithm. Computer simulations are presented to illustrate the performance of the new algorithm.

In this paper, we discuss digital watermarking techniques besed on modifying the spectral coefficient of an image, classified into quantization-based and correlation-based watermarking techniques. We first present a model of the watermark embedding and extracting processes and examine the robustness of the watermarking system against common image processing. Based on the result, we clarify the reason why detection errors occur in the watermark extracting process and give a method for evaluating the performance of the watermarking system. And then we study an improvement of the watermark extracting process using the deconvolution technique and present some concluding remarks in the last section.

Despite the enormous power of present-day computers, digital systems cannot respond to real-world events in real time. Biological systems, however, while being built with very slow chemical transistors, are very fast in such tasks like seeing, recognizing, and taking immediate actions. This paper discusses the issue of how we can build real-time intelligent systems directly on silicon. An intelligent VLSI system inspired by a psychological brain model is proposed. The system stores the past experience in the on-chip vast memory and recalls the maximum likelihood event to the current input based on the associative processor architecture. Although the system can be implemented in a CMOS digital technology, we are proposing here to implement the system using circuits operating in the analog/digital-merged decision making principle. Low-level processing is done in the analog domain in a fully parallel manner, which is immediately followed by a binary decision to yield answers in digital formats. Such a scheme would be very advantageous in achieving a high throughput computation under limited memory and computational resources usually encountered in mobile applications. Hardware-friendly algorithms have been developed for real-time image recognition using the associative processor architecture and some experimental results are demonstrated.

In this letter, an algorithm that estimates one of the most important channel parameters, maximum Doppler frequency, fD, is proposed. The algorithm uses phase variations of received pilot signals, which is strongly related with fD in a fading environment. In addition, a phase variation measurement method for binary phase shift keying (BPSK) modulated signals is also proposed and it makes possible to estimate fD from BPSK modulated information signals as well as unmodulated pilot signals. The results show that the proposed algorithm is very simple and shows good performance over wide Doppler frequency range.

It is of considerable interest to study the vortex behavior of a multiply connected superconductor for potential applications of vortex devices. Our sample is made of a type-I superconductor Pb and a capillary plate. The nominal sizes are 1-µm in hole diameter and 1.8-µm in lattice pitch. The microholes form triangular lattice while a superconducting network consists of a honeycomb lattice. When each hole accommodates a single vortex 0, an applied magnetic field becomes a nominal matching field (7.83 G). We measure the magnetization curve of sample by means of a SQUID (superconducting quantum interference device) magnetometer in the accurate small fields on the order of Gauss. We find a sharp magnetization peak at 8.2 G at temperatures near the critical temperature Tc.

We describe the logic design of a single-flux-quantum (SFQ) 22 unit switch. It is the main component of the SFQ Banyan packet switch we are developing that enables a switching capacity of over 1 Tbit/s. In this paper, we focus on the design of the controller in the unit switch. The controller does not have a simple "off-the-shelf" conventional circuit, like those used in shift registers or adders. To design such a complicated random logic circuit, we need to adopt a systematic top-down design approach. Using a graphical technique, we first obtained logic functions. Next, to use the deep pipeline architecture, we broke down the functions into one-level logic operations that can be executed within one clock cycle. Finally, we mapped the functions on to the physical circuits using pre-designed SFQ standard cells. The 22 unit switch consists of 59 logic gates and needs about 600 Josephson junctions without gate interconnections. We tested the gate-level circuit by logic simulation and found that it operates correctly at a throughput of 40 GHz.

The constant-Q based wavelet transform is the most effective means of quantitatively characterizing high frequency transient signals. This study develops a novel non constant-Q based multi-resolution transform (NCQM) and provides a precision analysis descriptor for both low and high frequency transients. The properties of this novel NCQM kernel are thoroughly examined and then the striking conceptual resemblance, energy conservation characteristic, and power spectrum close forms are derived. The rapid algorithm of NCQM is also presented and its excellent performance in noisy environments is demonstrated.

A flash analog-to-digital converter (ADC) that uses resonant-tunneling complex gates is proposed. The ternary quantizers, consisting of monostable-to-multistable transition logic (MML) circuits, convert the analog input signal into the ternary thermometer code. This code is then converted into the binary Gray-code output by a multiple-valued multiple-input monostable-bistable transition logic element (M2-MOBILE). By assuming InP-based resonant-tunneling diode (RTD) and heterojunction field-effect transistor technology, we have carried out SPICE simulation that demonstrates a 4-bit, 10-GS/s ADC operation. The input bandwidth, defined as a frequency at which the effective number of bit decreases by 0.5 LSB, was also estimated to be 500 MHz. Compact circuit configuration, which is due to the combination of MML and M2-MOBILE, reduces the device count and power dissipation by a factor of two compared with previous RTD-based ADCs.

We have fabricated and characterized two types of high-Tc planar SQUID gradiometers having different line width of pickup loops. The device worked in flux-locked loop (FLL) operation even in laboratory environment without any shielding. A magnetic field gradient resolution of a parallel-type device in a lightly shielded room was about 0.5 pT/cmHz1/2 at 1 kHz and 2 pT/cmHz1/2 at 1 Hz. The device was possible to record magnetocardiograms in a shielded room. QRS-complex peaks of about 10 pT PP/4mm are clearly observed. For a mesh-type device, the increase of low frequency noise in the open laboratory environment was less than that for a parallel-type.

Progress in the field of broadband access network and information appliances has led to the advent of a new network field called Home Network. In 1999, HomePNA2.0 using phone line was proposed, and we believe that it is one of the most promising solutions because of its cost-effectiveness. However, due to adaptation of the mature IEEE802.3 CSMA/CD technology used for Ethernet, it is not able to guarantee the QoS. We present the design, implementation and empirical evaluation of a new MAC protocol for the Home Network called HomeMAC. In this paper, the software based HomeMAC is implemented by programming the kernel space of FreeBSD. HomeMAC features a hybrid CSMA/CD-Timed Token protocol which combines the CSMA/CD for non-real-time traffic with timed token protocol for real-time traffic. In addition, by providing flexible bandwidth allocation based on QoS Level Table (QLT), HomeMAC can serve high QoS covering the whole offered load. From the results of evaluation of software implementation, we verify that HomeMAC can provide low delay, low loss, and low jitter to the real-time traffic by reservation of the bandwidth.

Recent advances make it possible to mitigate a number of drawbacks of conventional phase locked loops. These advances permit the design of phase tracking system with much improved characteristics that are sought after in modern communication system applications. A new phase tracking system is outlined which reduces the effects of VCO phase noise to an insignificant level. This fact permits extremely narrow bandwidth phase tracking systems to be realized, even when a VCO with poor phase noise characteristics is employed. The improvement in performance over conventional phase locked loops is analyzed. The new phase tracking system also has other benefits such as precise centre frequency and elimination of peaking in the transfer function. To implement the phase tracking system requires a frequency measurement. We outline a new highly integrated frequency measurement method suitable for narrow bandwidth applications. Experimental results from a prototype confirms theoretical results.

We present the design of dual rail Data Driven Self Timed (DDST) DEMUX and MUX circuits for 50 GHz operation. The chosen current density is 6.5 kA/cm2 and simulations show good margins for speeds exceeding 50 GHz. Our previously reported dual-rail on-chip test system is also scaled up for 50 GHz operation.

Data-Over-Cable Service Interface Specifications v1.1 (DOCSIS v1.1), developed for data transmissions over Hybrid Fiber Coaxial (HFC) networks, defines five upstream services for supporting per-flow Quality of Services (QoS). The cable modem termination system (CMTS) must periodically grant upstream transmission opportunities to the QoS flows based on their QoS parameters. However, packets may violate QoS requirements when several flows demand the same interval for transmission. This study proposes a two-phase, i.e., the scheduling sequence determination phase and the minislot assignment phase, minislot scheduling algorithm to reduce the QoS violation rate. In the scheduling sequence determination phase, the flow whose packets are most unlikely to violate QoS is scheduled first. Then, in the minislot assignment phase, the scheduler allocates to a flow the available interval where the likelihood of packet violation is minimum. Simulation results demonstrate that our scheduling algorithm can reduce the QoS violation rate by 80-35% over that of the first-come-first-serve-random-selection algorithm. It increases the utilization by 25% as well. The two-phase minislot scheduling algorithm can work within the DOCSIS v1.1 framework.

With the emerging technology of photonic networks, careful design becomes necessary to make most of the already installed fibre capacity. Appropriate numerical tools are readily available. Usually, these are based on the split-step Fourier method (SSFM), employing the fast Fourier transform (FFT). With N discretization points, the complexity of the SSFM is O(N log2N). For real-world wavelength division multiplexing (WDM) systems, the simulation time can be of the order of days, so any speed improvement would be most welcome. We show that the SSFM is a special case of the so-called collocation method with harmonic basis functions. However, for modelling nonlinear optical waveguides, various other basis function systems offer significant advantages. For calculating the propagation of single soliton-like impulses, a problem-adapted Gauss-Hermite basis leads to a strongly reduced computation time compared to the SSFM . Further, using a basis function system constructed from a scaling function, which generates a compactly supported wavelet, we developed a new and flexible split-step wavelet collocation method (SSWCM). This technique is independent of the propagating impulse shapes, and provides a complexity of the order O(N) for a fixed accuracy. For a typical modelling situation with up to 64 WDM channels, the SSWCM leads to significantly shorter computation times than the standard SSFM.

In this paper, we describe our SFQ circuit design and measurement carried out in SRL-ISTEC. We are studying an oversampling sigma-delta modulator and a counter-type decimation filter with multistage structure for developing AD converters for software-defined radio application. We are also developing a superconducting memory, whose peripheral circuits are constructed with SFQ circuits.

We report some leading research on superconducting devices in Taiwan. Research includes thin films, Josephson junctions, junction arrays and resonators etc. In device physics characteristics of Josephson junctions, junction array, and SQUIDs are reported. Applications of SQUIDs include: (1) studies of brain activities (magnetoencenphalogram) using multichannel low Tc SQUIDs system; (2) detection of weak magnetic fields (magnetocardiogragh, etc. ) using high-Tc SQUIDs; (3) nondestructive evaluation (NDE) of deep flaws using high-Tc SQUIDs. Research projects in the future in our group are briefly reported.

We present analytical and numerical results on the flux-quantum transitions in a three-junction superconducting quantum interference device (3J-SQUID) controlled by two RF signals. The 3J-SQUID has two superconducting loops, and the RF signals are magnetically coupled to the loops. Flux-quantum transitions in the 3J-SQUID loops can be controlled by utilizing the phase difference of the two RF signals. Under proper conditions, we can obtain a situation where one flux quantum passes through the 3J-SQUID per one cycle of the RF signals without DC current biasing, which results in a zero-crossing step on the current-voltage characteristics. In this paper, we first explain the operation principle by using a quantum state diagram of a 3J-SQUID. Next, we numerically simulate RF-induced transitions of the quantum states. A zero-crossing step on the current-voltage characteristics is demonstrated. We also investigate dependence of zero-crossing steps upon parameters of the 3J-SQUID and RF signals.

The major concern at a branch point in asynchronous transfer mode (ATM) networks for point-to-multipoint available bit rate (ABR) services is how to consolidate backward resource management (BRM) cells from each branch for a multicast connection. In this paper, we propose an efficient feedback consolidation algorithm based on an adaptive dynamic threshold (ADT) to eliminate consolidation noise and to reduce consolidation delay. The main idea of the ADT algorithm is that each branch point estimates the ABR traffic condition of the network through virtual queue estimation. Simulation results show that the proposed ADT algorithm can achieve a faster response in congestion status and a higher link utilization compared with the previous works.