Some undetectable stuck-at faults called the redundant faults are included in practical combinational circuits. The redundant fault does not affect the functional behavior of the circuit even if it exists. The redundant fault, however, causes undesirable effects to the circuit such as increase of delay time and decrease of testability of the circuit. It is considered that some redundant faults may cause the logical defects in the future. In this paper, firstly, we study the testability of the redundant fault in the combinational circuit by using delay effects. Secondly, we propose a method for generating a test-pair of a redundant fault by using an extended seven-valued calculus, called TGRF (Test-pair Generation for Redundant Fault). TGRF generates a dynamically sensitizable path for the target line which propagates the change in the value on the target line to a primary output. Finally, we show experimental results on the benchmark circuits under the assumptions of the unit delay and the fanout weighted delay models. It shows that test-pairs for some redundant faults are generated theoretically.

This paper describes a method for predicting the user's next utterances in spoken dialog based on the topic transition model, named TPN. Some templates are prepared for each utterance pair pattern modeled by SR-plan. They are represented in terms of five kinds of topic-independent constituents in sentences. The topic of an utterance is predicted based on the TPN model and it instantiates the templates. The language processing unit analyzes the speech recognition result using the templates. An experiment shows that the introduction of the TPN model improves the performance of utterance recognition and it drastically reduces the search space of candidates in the input bunsetsu lattice.

The performance of coded multi-pulse pulse position modulation (MPPM) consisting of m slots and 2 pulses, denoted as (m, 2) MPPM, with imperfect slot synchronization is analyzed. Convolutional codes and Reed-Solomon (RS) codes are employed for (m, 2) MPPM, and the bit error probability of coded (m, 2) MPPM in the presence of the timing offset is derived. In each coded (m, 2) MPPM, we compare the performance of some different code rate systems. Moreover, we compare the performance of both systems at the same information bit rate. It is shown that in both coded systems, the performance of code rate-1/2 coded (m, 2) MPPM is the best when the timing offset is small. Wheji the timing offset is somewhat large, however, uncoded (m, 2) MPPM is shown to perform better than coded (m, 2) MPPM. Further, convolutional coded (m, 2) MPPM with the constraint length k7 is shown to perform better than RS coded (m, 2) MPPM for the same code rate.

This paper proposes a new pitch prediction method for 4 kbps CELP (Code Excited LPC) speech coding with 20 msec frame, for the future ITU-T 4 kbps speech coding standardization. In the conventional CELP speech coding, synthetic speech quality deteriorates rapidly at 4 kbps, especially for female and children's speech with short pitch period. The pitch prediction performance is significantly degraded for such speech. The important reason is that when the pitch period is shorter than the subframe length, the simple repetition of the past excitation signal based on the estimated lag, not the pitch prediction, is usually carried out in the adaptive codebook operation. The proposed pitch prediction method can carry out the pitch prediction without the above approximation by utilizing the current subframe excitation codevector signal, when the pitch prediction parameters are determined. To further improve the performance, a split vector synthesis and perceptually spectral weighting method, and a low-complexity perceptually harmonic and spectral weighting method have also been developed. The informal listening test result shows that the 4 kbps speech coder with 20 msec frame, utilizing all of the proposed improvements, achieves 0.2 MOS higher results than the coder without them.

This paper describes new modeling methods combining neural network and hidden Markov model applicable to modeling a time series such as speech signal. The idea assumes that the sequence is nonstationary and is a nonlinear autoregressive process whose parameters are controlled by a hidden Markov chain. One is the model where a non-linear predictor composed of a multi-layered neural network is defined at each state, another is the model where a multi-layered neural network is defined so that the path from the input layer to the output layer is divided into path-groups each of which corresponds to the state of the Markov chain. The latter is an extended model of the former. The parameter estimation methods for these models are shown, and other previously proposed models--one called Neural Prediction Model and another called Linear Predictive HMM--are shown to be special cases of the NPHMM proposed here. The experimental result affirms the justification of these proposed models.

Recent works have shown that the size reduction of printed dipole antennas was possible thanks to a proper shaping of the radiating element. Following the same idea (choice of suitable shape), a shortened slot fed patch antenna exhibiting two step discontinuities, is described, analysed and optimized with a simple transmission line model. The shortening ratio (ρ) can reach 80% for matched antenna, printed on a substrate with a low dielectric constant (εr=2.2). The calculated results of input impedance are validated by experiment.

This paper proposes a functional video handling technique based on structured video. The video handling architecture, which includes a video data structure, file management structure, and visual interface structure, is introduced as the core concept of this technique. One of the key features of this architecture is that the newly proposed video indexing method is performed automatically based on image processing. The video data structure, which plays an important role in the architecture, has two kinds of data structures: content and node. The central idea behind these structures is to separate the video contents from the processing operations and to create links between them. Video indexes work as a backend mechanism in structuring video content. A prototype video handling system called the MediaBENCH, a hypermedia basic environment for computer and human interactions, which demonstrates the actual implementation of the proposed concept and technique, is described. Basic functions such as browsing and editing, which are achieved based on the architecture, exhibit the advantages of structured video handling. The concept and the methods proposed in this paper assure various video-computer applications, which will play major roles in the multimedia field.

This paper deals with an efficient radix-2 divider design theory that uses carry-propagation-free adders based on redundant binary{1, 0, 1} representation. In order to compute the division fast, we look ahead to the next step quotient-digit selection embedded in the current partial remainder calculation. The solution is a function of the four most significant digits of the current partial remainder, when scaling the divisor in the range [1, 9/8). In gate depth, this result is better than the higher radix-4 case without the look-ahead quotient-digit selection and the design is simple.

This paper proposes a practical training algorithm for artificial neural networks, by which both the optimally pruned model and the optimally trained parameter for the minimum prediction error can be found simultaneously. In the proposed algorithm, the conventional information criterion is modified into a differentiable function of weight parameters, and then it is minimized while being controlled back to the conventional form. Since this method has several theoretical problems, its effectiveness is examined by computer simulations and by an application to practical ultrasonic image reconstruction.

The recent progress of B-ISDN signaling systems has enabled networks to handle calls which require a wide variety of ATM connection sets. This paper is concerned with the circuit group which handles calls requesting asymmetric forward and backward multi-connections, and has the capability of both bandwidth negotiation and bandwidth reservation as a traffic control for enhancing call blocking performance. A model of the circuit group is first established focusing on the call level characteristics of the group, and then a method based on the reduced load approximation and an approximate analysis of a multirate group is proposed for calculating approximate blocking probabilities. The accuracy of the approximation method is evaluated numerically by comparing with an exact method and simulation. Further the impact of bandwidth negotiation and reservation on call blockings is examined based on numerical examples.

We present a design chart and a manufacturing process for mm-wave absorber consisting of two spacers (poly-carbonate) and two-resistive sheets (polyethylene terephthalate deposited with Indium Tin Oxide). The conventional design chart gives us necessary information to make a desirable absorber. Based on the design chart, a multi-layered type absorber was manufactured and it is concluded that a significant absorption level (-20dB) is attained at a wide-frequency range of 46-66GHz.

This paper describes an advanced rule-embedded neural network (RENN+) that has an extended framework for achieving a very tight integration of learning-based neural networks and rule-bases of existing if-then rules. The RENN+ is effective in pattern recognition with ill-posed conditions. It is basically composed of several component RENNs and an output RENN, which are three-layer back-propagation (BP) networks except for the input layer. Each RENN can be pre-organized by embedding the if-then rules through translation of the rules into logic functions in a disjunctive normal form, and can be trainded to acquire adaptive rules as required. A weight-modification-reduced learning algorithm (WMR) capable of standard regularization is used for the post-training to suppress excessive modification of the weights for the embedded rules. To estimate the effectiveness of the proposed RENN+, it was used for pattern recognition in a radar system for detection of buried pipes. This trial showed that a RENN+ with two component RENNs had good recognition capability, whereas a conventional BP network was ineffective.

Concerned is a spectral profile of electromagnetic (EM) emission from a signal line on a high-speed digital circuit. The authors have proposed and examined an a priori method to predict the peak frequencies on spectral profile of EM emission from printed circuit boards (PCBs). Profile of an EM spectrum is determined by the resonance of digital circuits. It is the purpose of this paper to investigate the parameters that determine the spectral profile of EM emission from a signal line on a PCS. In this paper, measurements and calculations of EM spectra were carried out for different load capacitances. EM emissions were measured with a small loop antenna at a 50mm from the surface of the PCB. Measured EM spectra had two peaks. Calculated EM spectra, which was based on transient current given by the analog simulator SPICE, had two peaks too. Results of calculations of EM spectra for different internal capacitances of an IC tell that lower peak frequency is determined by the resonance frequency of the resonant loop which is composed of an IC package and a decoupling capacitor. Comparison with measured EM spectra and calculated EM spectra for different load resistances tell that sharpness of the other peak depends on Q factor of a resonant loop which includes a signal line. Therefore the peak frequencies of EM emission spectrum can be predicted as two resonance frequencies of two resonant circuits.

We developed a parallel bordered-block-diagonal (BBD) matrix solution for parallel circuit simulation. In parallel circuit sumulation on a MIMD parallel computer, a circuit is partitioned into as many subcircuits as the processors of a parallel computer. Circuit partition produce a BBD matrix. In parallel BBD matrix solution, diagonal blocks are easily solved separately in each processor. It is difficult, however, to solve the interconnection (IC) submatrix of a BBD matrix effectively in parallel. To make matters worse, the more a circuit is partitioned into subcircuits for highly parallel circuit simulation, the larger the size of an IC submatrix becomes. From an examination, we found that an IC submatrix is more dense (about 30% of all entries are non-zeros) than a normal circuit matrix, and the non-zeros per row in an IC submatrix are almost constant with the number of subcircuits. To attain high-speed circuit simulation, we devised a data structure for BBD matrix processing and an approach to parallel BBD matrix solution. Our approach solves the IC submatrix in a BBD matrix as well as the diagonal blocks in parallel using all processors. In this approach, we allocate an IC submatrix in block-wise order rather than in dot-wise order onto all processors. Thus, we balance the processor perfomance with the communication capacity of a parallel computer system. When we changed the block size of IC submatrix allocation from dot-wise order to 88 block-wise order, the 88 block-wise order allocation almost halved the matrix solution time. The parallel simulation of a sample circuit with 3277 transistors was 16.6 times faster than a single processor when we used 49 processors.

In formal specification languages for parallel processes, such as CSP and LOTOS, algebraic laws for basic operators are provided that can be used to transform process expressions, and in particular, composition of processes can be calculated using these laws. Process composition can be used to simplify and improve the specification, and also to prove properties of the specification such as deadlock absence. We here test the practicality of process composition using CSP and suggest useful techniques, working in an example with nontrivial size and complexity. We emphasize that the size explosion of composed processes, caused by interleaving of the events of component processes, is a serious problem. Then we propose a technique, which we name two-way pipe, that can be used to reduce the size of the composed process, regarded as a program optimization at specification level.

In this study, after focussing on an energy (or intensity) scaled variable of acoustic systems, first, a new regression analysis method is theoretically proposed by introducing a multiplicative noise model suitable to the positively scaled stocastic system. Then, the effectiveness of the proposed method is confirmed experimentally by applying it to the actual acoustic data.

The networked reality is defined to be the virtual reality used in networks and using networks. The paper describes several levels of the networked reality and their applications.

This paper proposes a new environment for high-level VLSI design specification validation using "Algorithmic Debugging" and evaluates its benefits on three significant examples (a protocol processor, an 8-bit CPU, and a Prolog processor). A design is specified at a high-level using the structured analysis (SA) method, which is useful for analyzing and understanding the functionality to be realized. The specification written in SA is transformed into a logic programming language and is simulated in it. The errors (which terminate with an incorrect output in the simulation) included in the three large examples are efficiently located by answering junt a few queries from the algorithmic debugger. The number of interactions between the designer and the debugger is reduced by a factor of ten to a hundred compared to conventional simulation based validation methodologies. The correct SA specification can be automatically translated into a Register Transfer Level (RTL) specification suitable for logic synthesis. In this environment, a designer is freed from the tedious task of debugging a RTL specification, and can concentrate on the design itself. This environment promises to be an important step towards efficient high-level VLSI design specification validation.

This paper presents a method, called reduced scan shift, which generates short test sequences for full scan circuits. In this method, scan shift operations can be reduced, i.e., not all but part of flip-flops (FFs) are controlled and observed. This method, unlike partial scan methods, does not decrease fault coverage. In the reduced scan shift, test vectors for the combinational part of a circuit are fistly generated. Since short test sequence will be obtained from the small test vectors set, test compaction techniques are used in the test vector generation. For each test vector in the obtained test set, it is found which FFs should be controlled or observed. And then a scan chain is configured so that FFs more frequently required to be controlled (observed) can be located close to the scan input (output). After the scan chain is configured, the scan shift requirement is examined for the essential faults of each test vector. Essential fault is defined to be a fault which is detected by only one test vector but not other test vectors. The order of test vectors is carefully determined by comparing the scan control requirement of a test vector with the scan observation requirement of another test vector so that unnecessary scan shift operations only for controlling or observing FFs can be reduced. A method of determining the order of test vectors with state transition is additionally described. The effectiveness of the proposed method is shown by the experimental results for benchmark circuits.

With advances in the speed, bandwidth and reliability of telecommunications networks and in the performance of workstations, distributed processing has become widespread. Information sharing among distributed nodes and its mutual exclusion are of great importance for efficient distributed processing. This paper systematizes and quantitizes a shared memory called Data-Cyclic Shared Memory (DCSM) from the viewpoints of memory organization and access mode. In DCSM, the propagation delay of transmission lines and the data relaying delay in each node are used for information storage, and memory information encapsuled in the form of "memory cells" circulates infinitely in a logical ring type network. The distinctive feature of DCSM, in addition to the way data is stored, is that data and the access control are completely distributed, which contrasts with existing memory where both are centralized. Therefore, there are no performance bottlenecks caused by concentrating memory access. Distributed Shared Memory (DSM), which has a scheme similar to DCSM's, has also been proposed for distributed environments. In DSM, the data is also distributed but the control for accessing each data is centralized. From the viewpoints of memory organization and the access method, DCSM is very flexible. For instance, word length can be spatially varied by defining data size at each address, and each node can be equipped with mechanisms for special functions such as the content address specification and asynchronous report of change in contents. Because of this flexibility, it can be called a "software-defined memory." The analysis also reveals that DCSM has the disadvantages of large access delay and small memory capacity. The capacity can be enlarged by inserting FIFO type queues into the circulation network, and the delay can be shortened by circulating replicas of original memory cells. However, there is a trade off between the maximal capacity and the mean access time. DCSM has many potential applications, such as in the mutual exclusion control of distributed resources.