Nowadays, the World Wide Web is continuing to expand at an amazing rate as a medium for conducting business in addition to disseminating information, and Web users are remarkably increasing. Human activities in virtual space as the Web are producing large volumes of data, and Web data mining to extract information from Web data has become an important research area. In this paper, we examine the features of Web log data and propose a method for transaction identification. We also introduce a new problem of user segmentation and present a method for solving this problem.

A wavelet based algorithm for scalable video compression is described, with the main focus put on memory bandwidth reduction and efficient VLSI implementation. The proposed algorithm adopts a modified 2-D subband decomposition scheme in conjunction with a partial zerotree search for efficient Embedded Zerotree Wavelet coding. The experiment with the performance of the proposed algorithm in comparison with that of conventional DWT, MPEG-2, and JPEG demonstrates that the image quality of the proposed algorithm is consistently superior to that of JPEG, and our scheme can even outperform MPEG-2 in some cases, although it does not exploit the inter-frame redundancy. In spite of the performance inferiority to the conventional DWT, the proposed algorithm attains significant reduction of DWT memory requirements, enhancing a reasonable balance between implementation cost and image quality.

In this paper, characteristics of a digital system dedicated to the fast execution of the FDTD algorithm, widely used for electromagnetic simulation, are presented. Such system is conceived as a module communicating with a host personal computer via a PCI bus, and is based on a VLSI ASIC, which implements the "field-update" engine. The system structure is defined by means of a hardware description language, allowing to keep high-level system specification independent of the actual fabrication technology. A virtual implementation of the system has been carried out, by mapping such description in a standard-cell style on a commercial 0.35 µm technology. Simulations show that significant speed-up can be achieved, with respect to state-of-the-art software implementations of the same algorithm.

The Fundamental Law of Science and Technology and the Basic Plan of Science and Technology were established in Japan in 1995 and 1996, respectively and the second Basic Plan for Science and Technology R&D was established in April, 2001. In addition, as a part of Japanese government administrative reform, the Council for Science and Technology Policy was organized in the Cabinet Office and the most of the national research laboratories including the Communications Research Laboratory (CRL) have been restructured to the Independent Administrative Institution (IAI). This paper introduces first the relationship between the info-communications R&D and the national science and technology policy in Japan. Second, the R&D of CRL, IAI is introduced. Third, as a typical example of the wireless communications R&D, the research of wireless communication in CRL is shown in more detail in terms of terrestrial wireless/mobile communication system and satellite communication system. Finally the future prospect of such an R&D is shown briefly.

Two novel linearization processes in electro-absorption-modulator (EAM) are proposed and demonstrated. These two modulation schemes are used to compensate the nonlinear component of the EAM by controlling the DC bias voltages of the each EAM separately. The simulations on the nonlinearity of EAM and linearization process are performed in both time and frequency domains. From a serially cascaded modulation simulation, a reduction of 16 dB in IMD3, 45 dB in IMD5 and the following increase of 15 dB in linear dynamic rage (LDR) are achieved. In dual-parallel modulation experiment at 8 GHz, a reduction of 23 dB in IMD3 and the following increase of 15.1 dB in LDR of are achieved compared to those of a single EAM operation.

High-end telecommunication systems in the larger nationwide networks of the next decade will require routers having a packet switching throughput capacity of over 10 Tbps. In such future high-end routers, the packet switch, which is the biggest bottleneck of the router, will need higher processing speeds than semiconductor devices. We propose a high-end router system architecture using single flux quantum (SFQ) technology. This system consists of semiconductor line card units and an SFQ switch card unit. The features of this switch card architecture are (1) using internal speedup architecture to reduce effective loads in the network, (2) using a packet switch scheduler to attain non-blocking characteristics. This architecture can expand the switching capacity to a level greater than tens of Tbps scale, keeping with non-blocking characteristics.

SQUID (Superconducting QUantum Interference Device) Photoscanning is an analytical technique intended for the noninvasive evaluation of semiconductor wafers and device structures. This method is based on the detection of the magnetic field of photocurrents locally induced in the sample under investigation by a focused laser beam. The magnetic field is monitored by means of a sensitive SQUID magnetometer while scanning the sample surface with the laser beam. Doping inhomogeneities in electronic grade silicon, grain boundaries in solar silicon, and defects in photovoltaic device structures have been analyzed.

In this paper, we propose a turbo equalization scheme for GMSK signals with frequency detection. Although the channel is AWGN, there exists severe ISI (Inter-Symbol Interference) in the received signal due to the premodulation Gaussian baseband filter in the transmitter as well as the narrowband IF filter in the receiver. We regard these two filters as a real number inner convolutional encoder. The ISI equalizer for this inner encoder and the outer decoder for a RSC (Recursive Systematic Convolutional) code, are connected through a random (de-)interleaver. These inner and outer decoders generate the reliability values in terms of LLR (Log Likelihood Ratio), using MAP or SOVA algorithm with SISO (soft input and soft output). Moreover iterative decoding with the limitation of LLR values are employed between two decoders to achieve a turbo equalization for GMSK frequency detection. Through computer simulations, the proposed system shows the BER=10-5 at Eb/N0=8.8 dB, when we take BT=0.6 (IF filter bandwidth multiplied by symbol duration) with the iteration number of 3. This means 3.1 dB improvement compared with the conventional scheme where the inner ISI equalizer is concatenated with the outer hard decision Viterbi decoder.

This letter proposes a 3-D stereo endoscopic image processing system. Whereas a conventional 3-D stereo endoscopic system has simple monitoring functions, the proposed system gives doctors exact depth feelings by providing them depth value information, visualization, and stereo PACS viewer to aid an education, accurate diagnosis, a surgical operation, and to further apply in a robotic surgery.

A stabilized local oscillator is one of the key components for any radar system, especially for a Doppler radar in detecting slowly moving targets. Based on hybrid semiconductor/superconductor circuitry, the HTS local oscillator produces stable, low noise performance superior to that achieved with conventional technology. The device combines a high Q HTS sapphire cavity resonator (f=5.6 GHz) with a C-band low noise GsAs HEMT amplifier. The phase noise of the oscillator, measured by a HP 3048A noise measurement system, is -134 dBc/Hz at 10 kHz offset at 77 K.

A new low-voltage, all-in-one ESD (electrostatic discharging) protection circuit was designed. One such ESD protection unit is enough to protect each I/O pad against ESD stresses of all modes, i.e., from I/O to power supply and ground positively and negatively. This novel ESD circuit features adjustable trigger-voltage, i.e., 5 V to 60 V, with low turn-on threshold down to 5 V, symmetric active discharging channels in all directions, fast response time of 0.1 to 0.3 ns, and high ESD performance/area ratio of greater than 80 V per micrometer width. It was implemented in commercial BiCMOS technologies and achieved 14 kV human body model (HBM) and 15 kV air-gap IEC ESD protection levels. This compact ESD structure can not only provide adequate ESD protection, but also minimize the ESD-induced parasitic effects, which makes it a suitable ESD protection solution for mixed-signal and RF ICs in very deep sub-micron regime.

Scalabilities of bit rate and coding format in coded multimedia contents have become very important for the efficient use of network bandwidth and storage capacity with the recent availability of a wide variety of bandwidth and storage media. However, the conventional approach uses decompression and recompression processes to realize the above scalabilities, which require very expensive computations. In addition, a very large cache space is required for storing the decoded audio-video data. This paper describes three fast scalability methods for MPEG audio and video data, MPEG audio/video bit rate conversion and MPEG format conversion, in order to address these problems. As for the first scalability, MPEG audio coding bit rate conversions, we describe subband domain conversion using bandwidth limitation, requantization and a requantization reflecting phychoacoustic model. Four types of MPEG video bit rate conversion are described that use bandwidth limitation, out-loop requantization, in-loop requantization, and hybrid requantization. As for the format conversion, the fast baseband domain format conversion is performed using coding information such as motion vectors and coding types extracted from input coded video. The experimental results of several comparisons with the above scalabilities and conventional transcoding methods are also shown.

Recent advances make it possible to mitigate a number of drawbacks of conventional phase locked loops. These advances permit the design of phase tracking system with much improved characteristics that are sought after in modern communication system applications. A new phase tracking system is outlined which reduces the effects of VCO phase noise to an insignificant level. This fact permits extremely narrow bandwidth phase tracking systems to be realized, even when a VCO with poor phase noise characteristics is employed. The improvement in performance over conventional phase locked loops is analyzed. The new phase tracking system also has other benefits such as precise centre frequency and elimination of peaking in the transfer function. To implement the phase tracking system requires a frequency measurement. We outline a new highly integrated frequency measurement method suitable for narrow bandwidth applications. Experimental results from a prototype confirms theoretical results.

Data-Over-Cable Service Interface Specifications v1.1 (DOCSIS v1.1), developed for data transmissions over Hybrid Fiber Coaxial (HFC) networks, defines five upstream services for supporting per-flow Quality of Services (QoS). The cable modem termination system (CMTS) must periodically grant upstream transmission opportunities to the QoS flows based on their QoS parameters. However, packets may violate QoS requirements when several flows demand the same interval for transmission. This study proposes a two-phase, i.e., the scheduling sequence determination phase and the minislot assignment phase, minislot scheduling algorithm to reduce the QoS violation rate. In the scheduling sequence determination phase, the flow whose packets are most unlikely to violate QoS is scheduled first. Then, in the minislot assignment phase, the scheduler allocates to a flow the available interval where the likelihood of packet violation is minimum. Simulation results demonstrate that our scheduling algorithm can reduce the QoS violation rate by 80-35% over that of the first-come-first-serve-random-selection algorithm. It increases the utilization by 25% as well. The two-phase minislot scheduling algorithm can work within the DOCSIS v1.1 framework.

With the emerging technology of photonic networks, careful design becomes necessary to make most of the already installed fibre capacity. Appropriate numerical tools are readily available. Usually, these are based on the split-step Fourier method (SSFM), employing the fast Fourier transform (FFT). With N discretization points, the complexity of the SSFM is O(N log2N). For real-world wavelength division multiplexing (WDM) systems, the simulation time can be of the order of days, so any speed improvement would be most welcome. We show that the SSFM is a special case of the so-called collocation method with harmonic basis functions. However, for modelling nonlinear optical waveguides, various other basis function systems offer significant advantages. For calculating the propagation of single soliton-like impulses, a problem-adapted Gauss-Hermite basis leads to a strongly reduced computation time compared to the SSFM . Further, using a basis function system constructed from a scaling function, which generates a compactly supported wavelet, we developed a new and flexible split-step wavelet collocation method (SSWCM). This technique is independent of the propagating impulse shapes, and provides a complexity of the order O(N) for a fixed accuracy. For a typical modelling situation with up to 64 WDM channels, the SSWCM leads to significantly shorter computation times than the standard SSFM.

In this paper, we propose a new scheduling algorithm to achieve fault tolerance in multiprocessor systems. This algorithm first partitions a parallel program into subsets of tasks, based on the notion of height of a task graph. For each subset, the algorithm then duplicates and schedules the tasks in the subset successively. We prove that schedules obtained by the proposed algorithm can tolerate a single processor failure and show that the computational complexity of the algorithm is O(|V|4) where V is the set of nodes of a task graph. We conduct simulations by applying the algorithm to two kinds of practical task graphs (Gaussian elimination and LU-decomposition). The results of this experiment show that fault tolerance can be achieved at the cost of small degree of time redundancy, and that performance in the case of a processor failure is improved compared to a previous algorithm.

An LSI has been fabricated and measured to demonstrate feasibility of VDD-hopping scheme in an embedded system level by executing MPEG4 CODEC. In the VDD-hopping, supply voltage of a processor is dynamically controlled by a hardware-software cooperative mechanism depending on workload of the processor. When the workload is about a half, the VDD-hopping is shown to reduce power to less than a quarter compared to the conventional fixed-VDD scheme. The power saving is achieved without degrading real-time features of MPEG4 CODEC.

With increased size and issue-width, instruction issue queue becomes one of the most energy consuming units in today's superscalar microprocessors. This paper presents a novel architectural technique to reduce energy dissipation of adaptive issue queue, whose functionality is dynamically adjusted at runtime to match the changing computational demands of instruction stream. In contrast to existing schemes, the technique exploits a new freedom in queue design, namely the voltage per access. Since loading capacitance operated in the adaptive queue varies in time, the clock cycle budget becomes inefficiently exploited. We propose to trade-off the unused cycle time with supply voltage, lowering the voltage level when the queue functionality is reduced and increasing it with the activation of resources in the queue. Experiments show that the approach can save up to 39% of the issue queue energy without large performance and area overhead.

A method of learning for multi-layer artificial neural networks is proposed. The learning model is designed to provide an effective means of escape from the Backpropagation local minima. The system is shown to escape from the Backpropagation local minima and be of much faster convergence than simulated annealing techniques by simulations on the exclusive-or problem and the Arabic numerals recognition problem.

40 Gbit/s optical transceiver using a novel OTDM MUX module has been developed. OTDM (Optical-Time-Division-Multiplexing) MUX module, the core component of the transmitter, consisted of a optical splitter, two electro-absorption (EA) modulators and a combiner in a sealed small package. As the split optical paths run through the "air" in the module, greatly stable optical phase relation between bit-interleaved pulses could be maintained. With the OTDM MUX module, the selection between conventional Return-to-Zero (conventional-RZ) format and carrier-suppressed RZ (CS-RZ) format is performed by slightly changing the wavelength of laser-diode. In a receiver, 40 Gbit/s optical data train is optically demultiplexed to 10 Gbit/s optical train, before detected by the O/E receiver for 10 Gbit/s RZ format. Back-to-back MUX-DEMUX evaluations of the transceiver exhibited good sensitivities of under -30 dBm measured at 40 Gbit/s optical input to achieve the bit-error-rate (BER) of 10-9. Another unique feature of the transceiver system was a spectrum switch capability. The stable RZ and CS-RZ multiplexing operation was confirmed in the experiment. Once we adjust the 40 Gbit/s optical signal to CS-RZ format, the optical spectrum would maintain its CS spectrum shape for a long time to the benefit of the stable long transmission characteristics. In the recirculating loop experiment employing the OTDM MUX transceiver, the larger power margin was successfully observed with CS-RZ format than with conventional-RZ format, indicating that proper encoding of conventional-RZ and CS-RZ was realized with this prototype transceiver. In the case of CS-RZ format, the error free (BER < 10-9) transmission over 720 km was achieved with the long repeater amplifier span of 120 km.